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110 条记录 (耗时 0.023 秒)

    Semiconductor memory
    1.
    发明授权
    Semiconductor memory 有权

    公开(公告)号：US06621750B2

    公开(公告)日：2003-09-16

    申请号：US10155029

    申请日：2002-05-28

    申请人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Kota Hara ,  Katsuhiro Mori

    发明人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Kota Hara ,  Katsuhiro Mori

    IPC分类号： G11C700

    CPC分类号： G11C29/808 ,  G11C29/812 ,  G11C29/848

    摘要： A redundancy memory circuit stores a defect address indicating a defective memory cell row. A redundancy control circuit disables the defective memory cell row corresponding to the defect address stored in the redundancy memory circuit and enables a redundancy memory cell row in the memory block containing the defective memory cell row. Moreover, in the other memory blocks, the redundancy control circuit disables memory cell rows corresponding to the defective memory cell row and enables redundancy memory cell rows instead of these memory cell rows. Consequently, not only the memory block having the defective memory cell row but one of the memory cell rows in the other memory blocks is always also relieved. Thus, the redundancy memory circuit can be shared among all the memory blocks with a reduction in the number of redundancy memory circuits. As a result, the semiconductor memory can be reduced in chip size.

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US06529439B2

    公开(公告)日：2003-03-04

    申请号：US09789514

    申请日：2001-02-22

    申请人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

    发明人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

    IPC分类号： G11C800

    CPC分类号： G11C8/08 ,  G11C5/06

    摘要： A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.

    Memory circuit having compressed testing function
    5.
    发明授权
    Memory circuit having compressed testing function 有权
    存储电路具有压缩测试功能

    公开(公告)号：US06731553B2

    公开(公告)日：2004-05-04

    申请号：US10270196

    申请日：2002-10-15

    申请人： Shinya Fujioka ,  Waichiro Fujieda ,  Kota Hara

    发明人： Shinya Fujioka ,  Waichiro Fujieda ,  Kota Hara

    IPC分类号： G11C700

    CPC分类号： G11C29/40

    摘要： A multi-bit output configuration memory circuit comprises: a memory core having a normal cell array and a redundant cell array, which have a plurality of memory cells; N output terminals which respectively output N-bit output read out from the memory core; an output circuit provided between the output terminals and the memory core, which detects whether each L-bit output of the N-bit output (N=L×M) read out from said memory core matches or not and outputs a compressed output which becomes the output data in the event of a match while becomes a third state in the event of a non-match, to a first output terminal of the N output terminals. Responding to each of a plurality of test commands or the test control signals of the external terminals, the compressed output of the M groups of L-bit output is outputted in time shared.

    摘要翻译： 多比特输出配置存储器电路包括：具有正常单元阵列的存储器核心和具有多个存储单元的冗余单元阵列; N个输出端子，分别输出从存储器芯读出的N位输出; 输出电路，设置在输出端子和存储器核心之间，其检测从所述存储器芯片读出的N位输出（N = L×M）的每个L位输出是否匹配，并输出成为输出的压缩输出 在匹配的情况下的数据在不匹配的情况下变为第三状态时，输出到N个输出端的第一输出端。 响应多个测试命令或外部终端的测试控制信号中的每一个，M个组的L位输出的压缩输出以时间共享的形式被输出。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US06614712B2

    公开(公告)日：2003-09-02

    申请号：US10329669

    申请日：2002-12-27

    申请人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

    发明人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

    IPC分类号： G11C800

    CPC分类号： G11C8/08 ,  G11C5/06

    摘要： A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.

    Data transfer method and system
    7.
    发明授权
    Data transfer method and system 失效
    数据传输方式和系统

    公开(公告)号：US07730232B2

    公开(公告)日：2010-06-01

    申请号：US11113181

    申请日：2005-04-25

    申请人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

    发明人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0804 ,  G06F2212/2022 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C16/06 ,  G11C16/3454

    摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.

    摘要翻译： 提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。 传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从 响应于确认完成数据传送的传送状态。

    Semiconductor memory and burn-in test method of semiconductor memory
    8.
    发明授权
    Semiconductor memory and burn-in test method of semiconductor memory 有权
    半导体存储器的半导体存储器和老化测试方法

    公开(公告)号：US07200059B2

    公开(公告)日：2007-04-03

    申请号：US11260486

    申请日：2005-10-28

    申请人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

    发明人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

    IPC分类号： G11C29/00

    CPC分类号： G11C29/06 ,  G11C29/10 ,  G11C2029/0405 ,  G11C2029/1204 ,  G11C2029/3602

    摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.

    摘要翻译： 包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线 对，其中位线彼此平行的非扭转结构。 由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。 可以防止记忆单元的特性从老化测试过度恶化。 此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。 因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。 因此，可以降低测试成本。

    Semiconductor memory
    9.
    发明申请
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：US20050073903A1

    公开(公告)日：2005-04-07

    申请号：US10994630

    申请日：2004-11-23

    申请人： Shinya Fujioka ,  Yoshiaki Okuyama

    发明人： Shinya Fujioka ,  Yoshiaki Okuyama

    IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C7/00

    CPC分类号： G11C7/1051 ,  G11C7/1063 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076

    摘要： A refresh control circuit generates a refresh request in a predetermined cycle. A first burst control circuit outputs a predetermined number of strobe signals in accordance with an access command. A burst access operation is executed by an access command. A data input/output circuit successively inputs data to be transferred to a memory cell array or successively outputs data supplied from the memory cell array, in synchronization with the strobe signals. An arbiter determines which of a refresh operation or a burst access operation is to be executed first, when the refresh request and the access command conflict with each other. Therefore, the refresh operation and burst access operation can be sequentially executed without being overlapped. As a result, read data can be outputted at a high speed, and write data can be inputted at a high speed. That is, the data transfer rate can be improved.

    摘要翻译： 刷新控制电路以预定的周期生成刷新请求。 第一突发控制电路根据访问命令输出预定数量的选通信号。 通过访问命令执行突发存取操作。 数据输入/输出电路连续输入要传送到存储单元阵列的数据，或者与选通信号同步地连续输出从存储单元阵列提供的数据。 当刷新请求和访问命令彼此冲突时，仲裁器确定首先执行刷新操作或突发存取操作中的哪一个。 因此，可以顺序地执行刷新操作和突发存取操作而不重叠。 结果，可以高速地输出读取数据，并且可以高速地输入写入数据。 也就是说，可以提高数据传输速率。

    Semiconductor memory apparatus simultaneously accessible via multi-ports
    10.
    发明授权
    Semiconductor memory apparatus simultaneously accessible via multi-ports 失效
    半导体存储装置可以通过多端口同时访问

    公开(公告)号：US06868030B2

    公开(公告)日：2005-03-15

    申请号：US10345373

    申请日：2003-01-16

    申请人： Yoshiaki Okuyama ,  Shinya Fujioka

    发明人： Yoshiaki Okuyama ,  Shinya Fujioka

    IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C8/16 ,  G11C8/00

    CPC分类号： G11C8/16 ,  G11C5/025

    摘要： A dual-port semiconductor memory apparatus constructed by a core circuit and a plurality of ports, different row blocks of which in the same column block of the core circuit are simultaneously accessible. Since each of the ports is provided with a global data bus, different row blocks of the same column block can be accessed via both ports by selectively activating a column line corresponding to a port and another column line corresponding to another port.

    摘要翻译： 由核心电路和多个端口构成的双端口半导体存储装置，其核心电路的同一列块中的不同行块同时可访问。 由于每个端口设置有全局数据总线，所以可以通过选择性地激活与端口对应的列线和对应于另一端口的另一列线，通过两个端口来访问同一列块的不同行块。