利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

272 条记录 (耗时 0.054 秒)

    Device and method for image processing, program, and imaging apparatus
    11.
    发明申请
    Device and method for image processing, program, and imaging apparatus 有权
    用于图像处理，程序和成像装置的装置和方法

    公开(公告)号：US20100053366A1

    公开(公告)日：2010-03-04

    申请号：US12461406

    申请日：2009-08-11

    申请人： Hiroyuki Mizuno ,  Satoshi Terada

    发明人： Hiroyuki Mizuno ,  Satoshi Terada

    IPC分类号： H04N9/73

    CPC分类号： H04N9/735 ,  H04N5/144

    摘要： An image processing device includes a white balancing unit configured to perform white balancing on an image signal within a pull-in frame defined by the color temperature of a light source to output the resultant signal, and a control unit configured to, when the white balancing unit performs white balancing on an image signal obtained by capturing an image of a subject illuminated by light emitted from a light emitting device, adjust a region of the pull-in frame on the basis of color information of a light emission signal output from the light emitting device.

    摘要翻译： 一种图像处理装置，包括白平衡单元，被配置为对由光源的色温定义的拉入框内的图像信号执行白平衡，以输出结果信号;以及控制单元，被配置为当白平衡 通过拍摄由从发光装置发出的光照射的被摄体的图像而获得的图像信号进行白平衡，基于从光输出的发光信号的颜色信息来调整拉入框的区域 发光装置。

    Semiconductor device
    13.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07560975B2

    公开(公告)日：2009-07-14

    申请号：US11649766

    申请日：2007-01-05

    申请人： Kiyoo Itoh ,  Hiroyuki Mizuno

    发明人： Kiyoo Itoh ,  Hiroyuki Mizuno

    IPC分类号： H03K3/01

    CPC分类号： G11C5/146 ,  G05F3/205 ,  G11C5/147 ,  H01L27/092 ,  H02M3/073 ,  H03K19/0013 ,  H03K19/0016 ,  H03K19/00315

    摘要： The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.

    摘要翻译： 当电源接通时，在正常操作期间以及当电源电压被切断时，控制具有低阈值电压MOSFET的CMOS电路的阱电压。 因此，CMOS电路可以以更低的功耗稳定地运行，因为当将电源电压施加到CMOS电路时或者当电源电压被切断时，由于锁存减小，并且在正常操作期间亚阈值电流减小。

    PROCESSORS WITH BRANCH INSTRUCTION, CIRCUITS, SYSTEMS AND PROCESSES OF MANUFACTURE AND OPERATION
    14.
    发明申请
    PROCESSORS WITH BRANCH INSTRUCTION, CIRCUITS, SYSTEMS AND PROCESSES OF MANUFACTURE AND OPERATION 有权
    具有分支指令，电路，系统和制造和操作过程的处理器

    公开(公告)号：US20090106541A1

    公开(公告)日：2009-04-23

    申请号：US12236674

    申请日：2008-09-24

    申请人： Hiroyuki Mizuno ,  Yoann Foucher

    发明人： Hiroyuki Mizuno ,  Yoann Foucher

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3806 ,  G06F9/3004 ,  G06F9/30058 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/3844 ,  G06F9/3861

    摘要： An electronic processor is provided for use with a memory (2530) having selectable memory areas. The processor includes a memory area selection circuit (MMU) operable to select one of the selectable memory areas at a time, and an instruction fetch circuit (2520, 2550) operable to fetch a target instruction at an address from the selected one of the selectable memory areas. The processor includes an execution circuit (Pipeline) coupled to execute instructions from the instruction fetch circuit (2520, 2550) and operable to execute a first instruction for changing the selection by the memory area selection circuit (MMU) from a first one of the selectable memory areas to a second one of the selectable memory areas, the execution circuit (Pipeline) further operable to execute a branch instruction that points to a target instruction, access to the target instruction depending on actual change of selection to the second one of the memory areas; and the processor includes a logic circuit (3108, 3120, 3125, 3130, 3140) operable to ensure fetch of the target instruction in response to the branch instruction after actual change of selection. Other circuits, devices, systems, apparatus, and processes are also disclosed.

    摘要翻译： 电子处理器被提供用于具有可选存储区域的存储器（2530）。 处理器包括一个存储区域选择电路（MMU），可操作以一次选择一个可选择的存储区域;以及指令提取电路（2520,2550），可操作以从所选择的一个可选择的存储区域中的一个地址获取目标指令 记忆区域 该处理器包括一个执行电路（管线），它被执行来执行来自指令提取电路（2520,2550）的指令，并可操作以执行一个第一指令，用于通过存储区域选择电路（MMU）从可选择的第一个 存储器区域到可选存储区域中的第二个存储区域，执行电路（管道）还可操作以执行指向目标指令的转移指令，根据对存储器的第二存储器的选择的实际改变来访问目标指令 地区 并且处理器包括逻辑电路（3108,3120,3130,3130,3140），其可操作以在实际的选择改变之后响应于分支指令确保提取目标指令。 还公开了其它电路，装置，系统，装置和方法。

    Semiconductor integrated circuit with pulsed clock data latch
    15.
    发明授权
    Semiconductor integrated circuit with pulsed clock data latch 有权
    具有脉冲时钟数据锁存器的半导体集成电路

    公开(公告)号：US07443218B2

    公开(公告)日：2008-10-28

    申请号：US11476040

    申请日：2006-06-28

    申请人： Masafumi Onouchi ,  Yusuke Kanno ,  Hiroyuki Mizuno ,  Yasuhisa Shimazaki ,  Tetsuya Yamada

    发明人： Masafumi Onouchi ,  Yusuke Kanno ,  Hiroyuki Mizuno ,  Yasuhisa Shimazaki ,  Tetsuya Yamada

    IPC分类号： H03K3/00

    CPC分类号： H03K3/012 ,  H03K3/017 ,  H03K3/037

    摘要： A low power consumption in a semiconductor integrated circuit device can be achieved by reducing a glitch power in a flip-flop. In a pulse-generator-incorporated auto-clock-gating flip-flop in which data latch is performed by using a pulsed clock, input data is latched based on an output of a dynamic XOR circuit, which is a comparator circuit, during a period when the pulsed clock is at a high level, and the dynamic XOR circuit is cut off during a period when the pulsed clock is at a low level.

    摘要翻译： 可以通过减少触发器中的毛刺功率来实现半导体集成电路器件中的低功耗。 在其中通过使用脉冲时钟执行数据锁存的内置脉冲发生器的自动时钟门控触发器中，在一段时间内基于作为比较器电路的动态异或电路的输出来锁存输入数据 当脉冲时钟处于高电平时，并且在脉冲时钟处于低电平的时段期间动态异或电路被切断。

    Semiconductor integrated circuit
    16.
    发明申请
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US20080136502A1

    公开(公告)日：2008-06-12

    申请号：US11987073

    申请日：2007-11-27

    申请人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

    发明人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

    IPC分类号： G05F3/16 ,  G05F3/02

    CPC分类号： H01L27/0207 ,  G11C5/14 ,  G11C5/146 ,  G11C5/147 ,  H01L27/0928 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/0016 ,  H01L2924/00

    摘要： In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.

    摘要翻译： 为了提供满足快速操作和低功耗特性的诸如微处理器等的半导体IC单元，保持其高质量，本发明的半导体IC单元被构成为包括主电路（ LOG），其形成在半导体衬底上的晶体管和用于控制施加到衬底的电压的衬底偏置控制电路（VBC），并且主电路包括使用的开关晶体管（MN 1和MP 1） 用于控制施加到衬底的电压，并且从衬底偏置控制电路输出的控制信号被输入到每个开关晶体管的栅极，并且控制信号返回到衬底偏置控制电路。

    Semiconductor integrated circuit device
    18.
    发明申请
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US20070284619A1

    公开(公告)日：2007-12-13

    申请号：US11797034

    申请日：2007-04-30

    申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Naohiko Irie

    发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Naohiko Irie

    IPC分类号： H01L29/73

    CPC分类号： G01R31/318572 ,  G11C5/063 ,  G11C11/417 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K3/356008 ,  H03K3/35625 ,  H03K19/0016 ,  H01L2924/00

    摘要： In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

    摘要翻译： 在功率关闭时保留先前数据的低功耗模式下，其返回速度增加。 虽然可以考虑使用现有的数据保持触发器，但是这不是优选的，因为它增加了诸如扩大单元大小的面积开销。 用于电源关闭的数据保持的电源线由比通常的主电源线更细的布线形成。 优选地，用于数据保持电路的电力线被认为是信号线，并通过自动放置和安装进行布线。 为此，先前通过以与现有信号线相同的方式为小区提供终端来设计用于数据保持的电力线的终端。 电池线的附加布局不再需要，这使得现有的放置和布线工具能够减少面积和设计。

    Semiconductor device including a prediction circuit to control a power status control circuit which controls the power status of a function circuit
    19.
    发明授权
    Semiconductor device including a prediction circuit to control a power status control circuit which controls the power status of a function circuit 有权
    半导体器件包括用于控制功率状态控制电路的预测电路，其控制功能电路的电源状态

    公开(公告)号：US07222244B2

    公开(公告)日：2007-05-22

    申请号：US09932099

    申请日：2001-08-20

    申请人： Takayuki Kawahara ,  Takehiro Shimizu ,  Fumio Arakawa ,  Hiroyuki Mizuno ,  Takao Watanabe ,  Koichiro Ishibashi

    发明人： Takayuki Kawahara ,  Takehiro Shimizu ,  Fumio Arakawa ,  Hiroyuki Mizuno ,  Takao Watanabe ,  Koichiro Ishibashi

    IPC分类号： G06F1/32

    CPC分类号： H03K19/0016 ,  H03K19/1735

    摘要： A semiconductor device having a functional circuit block with predictive power controller is provided so as to construct a system LSI manufactured in a practicable number of design steps, which is extensible and in which power is reduced. The functional circuit block includes a prediction circuit and a predictive power shutdown circuit having a power status control circuit. The prediction circuit controls a power status of the functional circuit block by using the power status control circuit, based on input information thereto. When no information is inputted for a predetermined a period of time, the power status control circuit shifts from a power status of the functional circuit block to a low-power status.

    摘要翻译： 提供具有预测功率控制器的具有功能电路块的半导体器件，以便构建以可实施的数量的设计步骤制造的系统LSI，其是可扩展的并且功率减小。 功能电路块包括具有电源状态控制电路的预测电路和预测功率关断电路。 预测电路根据其输入信息，通过使用电源状态控制电路来控制功能电路块的电源状态。 当在预定的一段时间内没有输入信息时，电源状态控制电路从功能电路块的电源状态转换为低功率状态。

    Preventives/remedies for inflammatory airway diseases
    20.
    发明授权
    Preventives/remedies for inflammatory airway diseases 有权
    炎症性气道疾病的预防/补救措施

    公开(公告)号：US07214672B2

    公开(公告)日：2007-05-08

    申请号：US10451061

    申请日：2001-12-21

    申请人： Teruo Komoto ,  Hiroyuki Mizuno ,  Yoshinori Takahashi ,  Koichi Takahashi ,  Susumo Sato

    发明人： Teruo Komoto ,  Hiroyuki Mizuno ,  Yoshinori Takahashi ,  Koichi Takahashi ,  Susumo Sato

    IPC分类号： A61K31/56 ,  A61K31/58

    CPC分类号： C07J5/00 ,  A61K31/57 ,  A61K31/573 ,  C07J7/00

    摘要： A preventive and/or therapeutic agent for inflammatory respiratory tract diseases containing, as an active ingredient, a steroid derivative represented by the following formula (1): (wherein R represents a hydrogen atom, a halogen atom, a hydroxy group, or —OCOR1 (wherein R1 represents a linear or branched alkyl group which may be substituted by a halogen atom or a cycloalkyl group; a cycloalkyl group; or an aryl group)). These compounds can continuously suppress respiratory tract inflammation and respiratory tract hyperreaction and show a high site selectivity and little systemic effect when administered directly to the respiratory tract. By virtue of these characteristics, these compounds are remarkably useful in clinical medicine as highly safe preventive and/or therapeutic agents for inflammatory respiratory tract diseases which can be administered for a long period of time.

    摘要翻译： 一种炎性呼吸道疾病的预防和/或治疗剂，含有下式（1）表示的类固醇衍生物作为活性成分：（式中，R表示氢原子，卤素原子，羟基或-OCOR （其中R 1表示可被卤素原子或环烷基取代的直链或支链烷基;环烷基;或芳基））。 这些化合物可以连续抑制呼吸道炎症和呼吸道高反应，并且当直接施用于呼吸道时显示出高的选择性和很小的全身效应。 由于这些特征，这些化合物在临床医学中非常有用，作为可长期施用的炎症性呼吸道疾病的高度安全的预防和/或治疗剂。