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公开(公告)号：US07443218B2
公开(公告)日：2008-10-28
申请号：US11476040
申请日：2006-06-28
IPC分类号： H03K3/00
摘要： A low power consumption in a semiconductor integrated circuit device can be achieved by reducing a glitch power in a flip-flop. In a pulse-generator-incorporated auto-clock-gating flip-flop in which data latch is performed by using a pulsed clock, input data is latched based on an output of a dynamic XOR circuit, which is a comparator circuit, during a period when the pulsed clock is at a high level, and the dynamic XOR circuit is cut off during a period when the pulsed clock is at a low level.
摘要翻译： 可以通过减少触发器中的毛刺功率来实现半导体集成电路器件中的低功耗。 在其中通过使用脉冲时钟执行数据锁存的内置脉冲发生器的自动时钟门控触发器中，在一段时间内基于作为比较器电路的动态异或电路的输出来锁存输入数据 当脉冲时钟处于高电平时，并且在脉冲时钟处于低电平的时段期间动态异或电路被切断。
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公开(公告)号：US20070001734A1
公开(公告)日：2007-01-04
申请号：US11476040
申请日：2006-06-28
IPC分类号： H03K3/00
摘要： A low power consumption in a semiconductor integrated circuit device can be achieved by reducing a glitch power in a flip-flop. In a pulse-generator-incorporated auto-clock-gating flip-flop in which data latch is performed by using a pulsed clock, input data is latched based on an output of a dynamic XOR circuit, which is a comparator circuit, during a period when the pulsed clock is at a high level, and the dynamic XOR circuit is cut off during a period when the pulsed clock is at a low level.
摘要翻译： 可以通过减少触发器中的毛刺功率来实现半导体集成电路器件中的低功耗。 在其中通过使用脉冲时钟执行数据锁存的内置脉冲发生器的自动时钟门控触发器中，在一段时间内基于作为比较器电路的动态异或电路的输出来锁存输入数据 当脉冲时钟处于高电平时，并且在脉冲时钟处于低电平的时段期间动态异或电路被切断。
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公开(公告)号：US20100083011A1
公开(公告)日：2010-04-01
申请号：US12466696
申请日：2009-05-15
申请人： Masafumi ONOUCHI , Hiroyuki Mizuno , Yusuke Kanno , Makoto Saen
发明人： Masafumi ONOUCHI , Hiroyuki Mizuno , Yusuke Kanno , Makoto Saen
CPC分类号： G06F1/3203 , G06F1/10 , Y02D10/126
摘要： In a configuration provided with, for example, sixty four pieces of processor cores, an on-chip-memory, a bus commonly connected thereto, and others, the processor cores are operated by a power supply with low voltage and a clock with low frequency, and the bus is operated by a power supply with high voltage and a clock with high frequency. Each of the processor cores is provided with a bus interface and a frequency divider in order to absorb a power supply voltage difference and a frequency difference between the bus and each of them. The frequency divider generates the clock with low frequency from the clock with high frequency, and the bus interface is provided with a level shifting function, a data width converting function, a hand shaking function between the bus and the bus interface, and the like.
摘要翻译： 在具有例如六十四个处理器核心，片上存储器，与其连接的总线等的配置中，处理器核心由具有低电压的电源和具有低频率的时钟 ，总线由高电压电源和高频时钟驱动。 每个处理器内核都配有一个总线接口和一个分频器，以便吸收总线与它们中的每一个之间的电源电压差和频率差。 分频器从高频时钟产生低频时钟，总线接口提供电平转换功能，数据宽度转换功能，总线与总线接口之间的手抖功能等。
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4.发明申请SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD FOR CLOCK SIGNAL SYNCHRONIZATION 失效用于时钟信号同步的半导体集成电路和控制方法公开(公告)号：US20100117697A1
公开(公告)日：2010-05-13
申请号：US12615607
申请日：2009-11-10
申请人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
发明人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G06F1/10 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03L7/0818 , H03L7/089 , Y02D10/126 , Y02D10/172
摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
摘要翻译： 在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。 第一电路（FVA）使用第一电源电压（VDDA）进行操作。 第二电路（NFVA）使用第二电源电压（VDDB）进行操作。 可以在将时钟发送到这些电路的路径之间调整时钟延迟。 当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。 当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。 提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。
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5.发明授权Semiconductor integrated circuit and control method for clock signal synchronization 失效半导体集成电路和时钟信号同步控制方法公开(公告)号：US08350595B2
公开(公告)日：2013-01-08
申请号：US13438050
申请日：2012-04-03
申请人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
发明人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
CPC分类号： H03L7/0814 , G06F1/10 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03L7/0818 , H03L7/089 , Y02D10/126 , Y02D10/172
摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
摘要翻译： 在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。 第一电路（FVA）使用第一电源电压（VDDA）进行操作。 第二电路（NFVA）使用第二电源电压（VDDB）进行操作。 可以在将时钟发送到这些电路的路径之间调整时钟延迟。 当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。 当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。 提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。
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6.发明申请Semiconductor Integrated Circuit and Control Method for Clock Signal Synchronization 失效半导体集成电路和时钟信号同步控制方法公开(公告)号：US20120187993A1
公开(公告)日：2012-07-26
申请号：US13438050
申请日：2012-04-03
申请人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
发明人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G06F1/10 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03L7/0818 , H03L7/089 , Y02D10/126 , Y02D10/172
摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
摘要翻译： 在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。 第一电路（FVA）使用第一电源电压（VDDA）进行操作。 第二电路（NFVA）使用第二电源电压（VDDB）进行操作。 可以在将时钟发送到这些电路的路径之间调整时钟延迟。 当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。 当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。 提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。
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7.发明授权Semiconductor integrated circuit and control method for clock signal synchronization 失效半导体集成电路和时钟信号同步控制方法公开(公告)号：US08183899B2
公开(公告)日：2012-05-22
申请号：US12615607
申请日：2009-11-10
申请人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
发明人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , G06F1/10 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03L7/0818 , H03L7/089 , Y02D10/126 , Y02D10/172
摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
摘要翻译： 在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。 第一电路（FVA）使用第一电源电压（VDDA）进行操作。 第二电路（NFVA）使用第二电源电压（VDDB）进行操作。 可以在将时钟发送到这些电路的路径之间调整时钟延迟。 当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。 当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。 提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。
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公开(公告)号：US08829968B2
公开(公告)日：2014-09-09
申请号：US12555143
申请日：2009-09-08
IPC分类号： H03L5/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译： 具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。 第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。 转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。 转换电路（MIO1〜MIO4）通常用于连接电路块。
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公开(公告)号：US07813156B2
公开(公告)日：2010-10-12
申请号：US12242164
申请日：2008-09-30
IPC分类号： G11C5/06
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to bit line LBL.
摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到位线LBL的锁存型读出放大器SA。
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10.发明授权公开(公告)号：US07610572B2
公开(公告)日：2009-10-27
申请号：US11447168
申请日：2006-06-06
申请人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
发明人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
CPC分类号： H01L27/11898 , G06F17/5068 , G06F17/5072 , G11C11/419 , H01L23/48 , H01L23/50 , H01L23/528 , H01L27/00 , H01L27/02 , H01L27/0203 , H01L27/0207 , H01L27/11807 , H01L29/7835 , H01L2027/11881 , H01L2924/0002 , H03K3/0315 , H03K3/0375 , H03K17/16 , H01L2924/00
摘要： A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
摘要翻译： 一种具有控制信号系统的半导体集成电路装置，用于避免无法检查不确定信号传播防止电路的故障，以便于包括在自动化工具中的检查，以及便于芯片内的电源关闭控制。 在半导体集成电路器件中，功率关断优先级由独立电源域（A区至I区）提供。 还提供了当具有高优先级的电路被接通时，防止具有较低优先级的功率域被关断的方法。
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