LOW POWER OPERATIONAL AMPLIFIER TRIM OFFSET CIRCUITRY

    公开(公告)号:US20210167731A1

    公开(公告)日:2021-06-03

    申请号:US16701629

    申请日:2019-12-03

    Abstract: Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

    Attenuating common mode noise current in current mirror circuits

    公开(公告)号:US10317925B2

    公开(公告)日:2019-06-11

    申请号:US15473209

    申请日:2017-03-29

    Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.

    Fail-safe for shared pin
    14.
    发明授权

    公开(公告)号:US10211621B2

    公开(公告)日:2019-02-19

    申请号:US15087089

    申请日:2016-03-31

    Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.

    Inductor Detection
    15.
    发明申请
    Inductor Detection 审中-公开

    公开(公告)号:US20180011505A1

    公开(公告)日:2018-01-11

    申请号:US15710883

    申请日:2017-09-21

    Abstract: A power control integrated circuit (IC) chip can include a direct current (DC)-DC converter that outputs a switching voltage in response to a switching output enable signal. The power control IC chip can also include an inductor detect circuit that detects whether an inductor is conductively coupled to the DC-DC converter and a powered circuit component in response to an inductor detect signal. The power control IC chip can further include control logic that (i) controls the inductor detect signal based on an enable DC-DC signal and (ii) controls the switching output enable signal provided to the DC-DC converter and a linear output disable signal provided to a linear regulator based on a signal from the inductor detect circuit indicating whether the inductor is conductively coupled to the DC-DC converter and the powered circuit component.

    Detecting an inductor coupled to a power control circuit

    公开(公告)号:US09804617B2

    公开(公告)日:2017-10-31

    申请号:US15088612

    申请日:2016-04-01

    Abstract: A power control integrated circuit (IC) chip can include a direct current (DC)-DC converter that outputs a switching voltage in response to a switching output enable signal. The power control IC chip can also include an inductor detect circuit that detects whether an inductor is conductively coupled to the DC-DC converter and a powered circuit component in response to an inductor detect signal. The power control IC chip can further include control logic that (i) controls the inductor detect signal based on an enable DC-DC signal and (ii) controls the switching output enable signal provided to the DC-DC converter and a linear output disable signal provided to a linear regulator based on a signal from the inductor detect circuit indicating whether the inductor is conductively coupled to the DC-DC converter and the powered circuit component.

    Low dropout voltage regulator circuits
    20.
    发明授权
    Low dropout voltage regulator circuits 有权
    低压差稳压电路

    公开(公告)号:US09477246B2

    公开(公告)日:2016-10-25

    申请号:US14183739

    申请日:2014-02-19

    CPC classification number: G05F1/575

    Abstract: In an embodiment, a voltage regulator is disclosed. The voltage regulator circuit includes a switch, a first feedback circuit and a second feedback circuit. The switch is configured to receive an input signal at a first terminal and an error signal at a second terminal and configured to generate an output signal at a third terminal. The first feedback circuit includes a first transistor and a second transistor configured to control the error signal at the second terminal of the switch in response to a difference between the output signal and a reference signal. The second feedback circuit is configured to sense the error signal and generate a tail current at the second node and the fourth node to maintain substantially equal currents in the first transistor and the second transistor, respectively, thereby causing a voltage of the output signal as substantially equal to a voltage of the reference signal.

    Abstract translation: 在一个实施例中,公开了一种电压调节器。 电压调节器电路包括开关,第一反馈电路和第二反馈电路。 该开关被配置为在第一终端处接收输入信号,并在第二终端处接收错误信号,并且被配置为在第三终端处产生输出信号。 第一反馈电路包括第一晶体管和第二晶体管,其被配置为响应于输出信号和参考信号之间的差异来控制开关的第二端处的误差信号。 第二反馈电路被配置为感测误差信号并在第二节点和第四节点处产生尾电流,以在第一晶体管和第二晶体管中分别维持基本相等的电流,从而使输出信号的电压基本上 等于参考信号的电压。

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