Constant amplitude ramp generator
    11.
    发明授权

    公开(公告)号:US11552624B1

    公开(公告)日:2023-01-10

    申请号:US17491343

    申请日:2021-09-30

    Abstract: In described examples of a ramp circuit, a first terminal of a capacitor is coupled to a ramp terminal and a second capacitor terminal is coupled to a return terminal. A charge source has an input terminal coupled to a supply terminal and a charge output terminal. A resistor has a first terminal coupled to the return terminal. A first switch is coupled between the ramp terminal and a second terminal of the resistor. A second switch is coupled between the charge output terminal and the ramp terminal.

    Switch-mode power supply with load current based throttling

    公开(公告)号:US11552565B2

    公开(公告)日:2023-01-10

    申请号:US16860511

    申请日:2020-04-28

    Abstract: A switch-mode power supply circuit includes a low-side switching transistor, a high-side switching transistor, a low-side current sensing circuit, and a gate driver circuit. The low-side current sensing circuit is coupled to the low-side switching transistor and is configured to sense a current flowing through the low-side switching transistor. The gate driver circuit is coupled to the low-side current sensing circuit and the high-side switching transistor. The gate driver circuit is configured to generate a signal having a first drive strength to switch the high-side switching transistor based on current flowing through the low-side switching transistor being less than a threshold current, and to generate a signal having a second drive strength to switch the high-side switching transistor based on current flowing through the low-side switching transistor being greater than the threshold current. The first drive strength is greater than the second drive strength.

    METHODS AND APPARATUS FOR ADAPTIVE TIMING FOR ZERO VOLTAGE TRANSITION POWER CONVERTERS

    公开(公告)号:US20170302149A1

    公开(公告)日:2017-10-19

    申请号:US15396471

    申请日:2016-12-31

    CPC classification number: H02M3/158 H02M1/08 H02M2001/0054 H03K17/04123

    Abstract: A method of controlling a power converter, including executing a plurality of cycles, including: turning on a first switch during a first period, the first switch coupled to a power supply and a switch node; turning on a second switch during a second period, the second switch coupled to the switch node; turning on a third switch at a first time during the second period and turning the third switch off at a second time after the second period by a first open signal including a high discharge signal followed by a lower discharge signal, the third switch coupled to an auxiliary node and to a second inductor coupled to the auxiliary node; and turning on a fourth switch at a third time after the second time and turning the fourth switch off during the first period of a succeeding cycle, the fourth switch coupled to the auxiliary node.

    Semiconductor process variation detector

    公开(公告)号:US11476760B2

    公开(公告)日:2022-10-18

    申请号:US16927558

    申请日:2020-07-13

    Abstract: In some examples, a system includes a voltage source terminal, a voltage reference terminal, a field effect transistor (FET), a current source, a comparator, and adjustment circuitry. The FET has a gate terminal and a non-gate terminal, the gate terminal coupled to the voltage source terminal. The current source is coupled to the non-gate terminal. The comparator has a comparator output and first and second comparator inputs, the first comparator input coupled to the non-gate terminal, and the second comparator input coupled to the voltage reference terminal. The adjustment circuitry has a circuitry input and a circuitry output, the circuitry input coupled to the comparator output, and the adjustment circuitry configured to adjust the circuitry output responsive to the circuitry input, in which the adjustment reduces a drive strength of the circuit.

    PRIMARY SIDE BURST MODE CONTROLLER FOR LLC CONVERTER

    公开(公告)号:US20210257917A1

    公开(公告)日:2021-08-19

    申请号:US17308634

    申请日:2021-05-05

    Abstract: Embodiments include systems, methods, and apparatuses for controlling off-time during a burst mode in an LLC converter. In one embodiment, a circuit comprises an LLC converter having a primary side and a burst mode controller, the burst mode controller configured to monitor, on the primary side of the LLC converter, electrical current, and in response to a determination that the electrical current is below a first threshold, increase an off-time for switches in the LLC converter and in response to a determination that the electrical current is above a second threshold that is higher than the first threshold, decrease the off-time for the switches in the LLC converter.

    Adaptive synchronous rectification in a voltage converter

    公开(公告)号:US11018582B2

    公开(公告)日:2021-05-25

    申请号:US16399793

    申请日:2019-04-30

    Abstract: A circuit includes a first transistor and a second transistor coupled to the first transistor at a switch node and to a ground node. An estimator circuit receives a first signal to control an on and off state of the first transistor. The estimator circuit generates a second signal to control the on and off state of the second transistor. The second signal has a pulse width based on a pulse width of the first signal. A clocked comparator includes a clock input, a first input, and a second input. The first input receives a voltage indicative of a voltage of the switch node. The second input is coupled to a ground node. The clock input receives a third signal indicative of the second signal. The clocked comparator generates a comparator output signal. The estimator circuit adjusts the pulse width of the second signal based on the comparator output signal.

    THREE-LEVEL CONVERTER USING AN AUXILIARY SWITCHED CAPACITOR CIRCUIT

    公开(公告)号:US20200021196A1

    公开(公告)日:2020-01-16

    申请号:US16584610

    申请日:2019-09-26

    Abstract: In a described example, an apparatus includes a first switch coupled between a terminal for receiving an input voltage and a top plate node, and having a first control terminal; a second switch coupled between the top plate node and a switching node, and having a second control terminal; a third switch coupled between the switching node and a bottom plate node and having a third control terminal; a fourth switch coupled between the bottom plate node and a ground terminal, and having a fourth control terminal; a flying capacitor coupled between the top plate node and the bottom plate node; a fifth switch coupled between the top plate node and an auxiliary node; a sixth switch coupled between the auxiliary node and the bottom plate node; and an auxiliary capacitor coupled between the auxiliary control terminal and a ground terminal.

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