公开(公告)号：US5539688A

公开(公告)日：1996-07-23

申请号：US444313

申请日：1995-05-18

申请人： Tom D. Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

发明人： Tom D. Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/24 ,  G11C16/06

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

摘要翻译： 用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位 要编程的FLASH EPROM晶体管单元的栅极和源极。 提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。 字线电压是变化的，而源电压保持恒定。 通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。 另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。 此外，调整正在编程的单元上的负载以提高编程速度。

公开(公告)号：US5618742A

公开(公告)日：1997-04-08

申请号：US329487

申请日：1994-10-26

申请人： Fuchia Shone ,  Tom D.-H. Yiu ,  Tien-Ler Lin

发明人： Fuchia Shone ,  Tom D.-H. Yiu ,  Tien-Ler Lin

IPC分类号： G08G1/017 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11519 ,  G08G1/017 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

摘要： Contactless flash EPROM cell and array designs, and methods for fabricating the same result in dense, segmentable flash EPROM chips. Also, an extended floating gate structure, and method for manufacturing the extended floating gate allow for higher capacitive coupling ratios in flash EPROM circuitry with very small design rules. The floating gates are extended in a symmetrical fashion in a drain-source-drain architecture, so that each pair of columns of cells has a floating gate which is extended in opposite directions from one another. This allows one to take advantage of the space on the cell normally consumed by the isolation regions, to extend the floating gates without increasing the layouts of the cells. Also, an easily scalable design is based on establishing conductive spacers on the sides of floating gate deposition layers which are used for self-alignment of the source and drain. According to this structure, a floating gate deposition is first laid down and used for establishing self-aligned source and drain diffusion regions. After deposition of the source and drain, conductive spacers are deposited on the sides of the first floating gate structure. These conductive spacers can be deposited in a symmetrical fashion, and are easily scalable to large scale arrays of flash EPROM designs.

摘要翻译： 非接触式闪存EPROM单元和阵列设计及其制造方法产生致密的，可分割的闪存EPROM芯片。 此外，扩展浮动栅极结构和用于制造扩展浮栅的方法允许具有非常小的设计规则的闪存EPROM电路中的较高的电容耦合比。 浮置栅极以排列 - 源极 - 漏极结构中的对称方式延伸，使得每对单元电池具有彼此相反方向延伸的浮动栅极。 这允许人们利用通常由隔离区域消耗的单元上的空间来扩展浮动栅极而不增加单元的布局。 此外，易于扩展的设计是基于在用于源极和漏极的自对准的浮栅沉积层的侧面上建立导电间隔物。 根据该结构，首先放置浮置栅极沉积并用于建立自对准的源极和漏极扩散区域。 在沉积源极和漏极之后，导电间隔物沉积在第一浮栅结构的侧面上。 这些导电间隔物可以以对称的方式沉积，并且易于扩展到闪存EPROM设计的大规模阵列。

公开(公告)号：US5956273A

公开(公告)日：1999-09-21

申请号：US106525

申请日：1998-06-29

申请人： Tien-Ler Lin ,  Fuchia Shone

发明人： Tien-Ler Lin ,  Fuchia Shone

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/24 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

公开(公告)号：US5615153A

公开(公告)日：1997-03-25

申请号：US444314

申请日：1995-05-18

申请人： Tom D. Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

发明人： Tom D. Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/24 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

摘要翻译： 用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位 要编程的FLASH EPROM晶体管单元的栅极和源极。 提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。 字线电压是变化的，而源电压保持恒定。 通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。 另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。 此外，调整正在编程的单元上的负载以提高编程速度。

公开(公告)号：US5526307A

公开(公告)日：1996-06-11

申请号：US325467

申请日：1994-10-26

申请人： Tom D. Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ray L. Wan

发明人： Tom D. Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ray L. Wan

IPC分类号： G08G1/017 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： G08G1/017 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521

摘要： Contactless flash EPROM cell and array designs, and methods for fabricating the same result in a dense, segmentable flash EPROM chip. The flash EPROM cell is based on a drain-source-drain configuration, in which the single source diffusion is shared by two columns of transistors. The module includes a memory array having at least M rows and 2N columns of flash EPROM cells. M word lines, each coupled to the flash EPROM cells in one of the M rows of the flash EPROM cells, and N global bit lines are included. Data in and out circuitry is coupled to the N global bit lines which provide for reading and writing data in the memory array. Selector circuitry, coupled to the 2N columns of flash EPROM cells, and to the N global bit lines, provides for selective connection of two columns of the 2N columns to each of the N global bit lines so that access to the 2N columns of flash EPROM cells by the data in and out circuitry is provided across N global bit lines. The semiconductor substrate has a first conductivity type, a first well in the substrate of a second conductivity type, and a second well of the first conductivity type in the first well. The flash EPROM cells are made in the second well to allow application of a negative potential to at least one of the source and drain during an operation to charge the floating gate in the cells.

摘要翻译： PCT No.PCT / US94 / 10331 Sec。 371日期：1994年10月26日 102（e）1994年10月26日PCT 1994年9月13日提交PCT无连接闪存EPROM单元和阵列设计及其制造方法产生密集的可分割闪存EPROM芯片。 闪存EPROM单元基于漏 - 源 - 漏配置，其中单个源扩散由两列晶体管共享。 该模块包括具有至少M行和2N列闪存EPROM单元的存储器阵列。 M字线各自耦合到闪存EPROM单元的M行之一中的闪存EPROM单元和N个全局位线。 数据输入和输出电路耦合到提供在存储器阵列中读取和写入数据的N个全局位线。 耦合到2N列的闪存EPROM单元和N个全局位线的选择器电路提供了将2N列的两列选择性地连接到N个全局位线中的每一个，使得访问闪存EPROM的2N列 通过数据输入和输出电路的单元被提供在N个全局位线之间。 半导体衬底具有第一导电类型，第二导电类型的衬底中的第一阱和第一阱中第一导电类型的第二阱。 闪存EPROM单元在第二阱中制造，以允许在对单元中的浮置栅极充电的操作期间向源极和漏极中的至少一个施加负电位。

公开(公告)号：US5532960A

公开(公告)日：1996-07-02

申请号：US371361

申请日：1995-01-11

申请人： Tien-Ler Lin ,  Liang Chao

发明人： Tien-Ler Lin ,  Liang Chao

IPC分类号： G11C5/14 ,  G11C16/30 ,  H02M3/07 ,  G11C7/00

CPC分类号： H02M3/07 ,  G11C16/30 ,  G11C5/145

摘要： A circuit is provided for supplying a negative high voltage to an integrated circuit from a high positive voltage source V.sub.PP. The negative voltage is applied to a plurality of FLASH electrically erasable programmable read only memory (EPROM) cells. The circuit includes an oscillator coupled to a voltage converter which provides a periodic signal. The periodic signal is coupled to a charge pump including three P-channel type transistors to produce the negative voltage. The source and drain of the first transistor is coupled to the periodic signal. The second transistor's gate and drain is coupled to a reference ground potential with the source coupled to the first transistor's gate. Finally, the third transistor's drain and gate is coupled to the first transistor's gate and the third transistor's source outputs negative voltage to floating gates of the plurality of FLASH EPROM cells during an erase operation. Further, the negative voltage generated is relatively precise, so no regulation is required.

摘要翻译： 提供一种用于从高正电压源VPP向集成电路提供负高电压的电路。 负电压被施加到多个FLASH电可擦除可编程只读存储器（EPROM）单元。 电路包括耦合到提供周期性信号的电压转换器的振荡器。 周期信号耦合到包括三个P沟道型晶体管的电荷泵以产生负电压。 第一晶体管的源极和漏极耦合到周期性信号。 第二晶体管的栅极和漏极耦合到参考地电位，源极耦合到第一晶体管的栅极。 最后，第三晶体管的漏极和栅极耦合到第一晶体管的栅极，并且第三晶体管的源极在擦除操作期间向多个FLASH EPROM单元的浮动栅极输出负电压。 此外，产生的负电压是相对精确的，因此不需要调节。

公开(公告)号：US5414664A

公开(公告)日：1995-05-09

申请号：US108662

申请日：1993-08-31

申请人： Tien-Ler Lin ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Gilbert Sung

发明人： Tien-Ler Lin ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Gilbert Sung

IPC分类号： G11C16/16 ,  G11C16/34 ,  G11C7/00 ,  G11C16/00

CPC分类号： G11C16/3445 ,  G11C16/16 ,  G11C16/344

摘要： A FLASH EPROM device includes a memory array organized into a plurality of blocks of memory cells. An energizing circuit applies energizing voltages to the blocks of memory cells to read and program addressed cells, and to erase selected blocks or the whole memory array. An erase verify circuit separately verifies erasure of blocks in the plurality of block memory cells. Control logic controls the energizing circuit to re-erase blocks which fail erase verify. The control logic includes a plurality of block erase flags which correspond to respective blocks of memory cells in the array. The erase verify is responsive to the block erase flags to verify only those blocks having a set block erase flag. If the block passes erase verify, then the block erase flag is reset. Only those blocks having a set block erase flag after the erase verify operation are re-erased. To support this operation, the circuit also includes the capability of erasing only a block of the memory array at a time.

摘要翻译： PCT No.PCT / US93 / 05146 Sec。 371日期：1993年8月31日 102（e）日期1993年8月31日PCT PCT日期为1993年5月28日。FLASH EPROM装置包括组织成多个存储单元块的存储器阵列。 激励电路向存储器单元的块施加通电电压以读取和编程寻址单元，并擦除所选择的块或整个存储器阵列。 擦除验证电路分别验证多个块存储器单元中的块的擦除。 控制逻辑控制通电电路重新擦除擦除验证失败的块。 控制逻辑包括与阵列中的存储器单元的相应块对应的多个块擦除标志。 擦除验证响应于块擦除标志以仅验证具有设置块擦除标志的那些块。 如果块通过擦除验证，则块擦除标志被复位。 在擦除验证操作之后，仅具有设置块擦除标志的块被重新擦除。 为了支持这种操作，该电路还包括一次仅擦除存储器阵列的能力。

公开(公告)号：US06507514B1

公开(公告)日：2003-01-14

申请号：US09974227

申请日：2001-10-10

申请人： Cheng-Chung Tsao ,  Tien-Ler Lin

发明人： Cheng-Chung Tsao ,  Tien-Ler Lin

IPC分类号： G11C1604

CPC分类号： G11C8/06 ,  G11C8/12 ,  G11C8/18 ,  G11C16/08

摘要： An integrated circuit chip suitable for use in either a single chip packaged configuration or a multi-chip packaged configuration is disclosed. The chip has a conventional memory circuit portion and a control circuit portion. In operation as a single chip packaged configuration, the control circuit portion is inactive. In a multi-chip packaged configuration, the control circuit serves to prolong the activation of the currently addressed memory chip, while delaying the activation of the memory chip which is to be addressed in the next memory address cycle.

摘要翻译： 公开了适用于单芯片封装结构或多芯片封装结构的集成电路芯片。 芯片具有传统的存储电路部分和控制电路部分。 在作为单芯片封装配置的操作中，控制电路部分是无效的。 在多芯片封装配置中，控制电路用于延长当前寻址的存储器芯片的激活，同时延迟在下一个存储器地址周期中要寻址的存储器芯片的激活。

公开(公告)号：US06366519B1

公开(公告)日：2002-04-02

申请号：US08624389

申请日：1996-04-05

申请人： Chun-Hsiung Hung ,  Tien-Ler Lin ,  Kota Soejima ,  Satoshi Matsubara

发明人： Chun-Hsiung Hung ,  Tien-Ler Lin ,  Kota Soejima ,  Satoshi Matsubara

IPC分类号： G11C1300

CPC分类号： G11C16/30 ,  G11C5/145 ,  G11C5/147

摘要： A charge pump circuit which generates an output voltage at a selected level, but variations in the current supplied to the charge pump are limited, and variations in the output current generated by the charge pump are limited. The charge pump circuit is coupled to a power supply which has a supply voltage which varies over a specified range. It includes a first charge pump that generates a reference voltage higher than the supply voltage in response to the supply voltage. A circuit, coupled to the first charge pump and responsive to the reference voltage generates a regulated supply voltage. A second charge pump generates a controlled output voltage in response to the regulated supply voltage. The regulated supply voltage is used by pump clock drivers and as a pump reference supply for the second charge pump.

摘要翻译： 产生选定电平的输出电压但供给电荷泵的电流的变化的电荷泵电路受到限制，电荷泵产生的输出电流的变化受到限制。 电荷泵电路耦合到具有在指定范围内变化的电源电压的电源。 它包括第一电荷泵，其产生响应于电源电压而高于电源电压的参考电压。 耦合到第一电荷泵并响应于参考电压的电路产生稳定的电源电压。 第二电荷泵响应于稳定的电源电压产生受控的输出电压。 调节电源电压由泵浦时钟驱动器和第二个电荷泵的泵参考电源使用。

公开(公告)号：US5596530A

公开(公告)日：1997-01-21

申请号：US383726

申请日：1995-02-02

申请人： Tien-Ler Lin ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Gilbert Sung

发明人： Tien-Ler Lin ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Gilbert Sung

IPC分类号： G11C16/16 ,  G11C16/34 ,  G11C7/00 ,  G11C16/00

CPC分类号： G11C16/3445 ,  G11C16/16 ,  G11C16/344

摘要： A FLASH EPROM device includes a memory array organized into a plurality of blocks of memory cells. An energizing circuit applies energizing voltages to the blocks of memory cells to read and program addressed cells, and to erase selected blocks or the whole memory array. An erase verify circuit separately verifies erasure of blocks in the plurality of block memory cells. Control logic controls the energizing circuit to re-erase blocks which fail erase verify. The control logic includes a plurality of block erase flags which correspond to respective blocks of memory cells in the array. The erase verify is responsive to the block erase flags to verify only those blocks having a set block erase flag. If the block passes erase verify, then the block erase flag is reset. Only those blocks having a set block erase flag after the erase verify operation are re-erased. To support this operation, the circuit also includes the capability of erasing only a block of the memory array at a time.

摘要翻译： FLASH EPROM装置包括组织成多个存储单元块的存储器阵列。 激励电路向存储器单元的块施加通电电压以读取和编程寻址单元，并擦除所选择的块或整个存储器阵列。 擦除验证电路分别验证多个块存储器单元中的块的擦除。 控制逻辑控制通电电路重新擦除擦除验证失败的块。 控制逻辑包括与阵列中的存储器单元的相应块对应的多个块擦除标志。 擦除验证响应于块擦除标志以仅验证具有设置块擦除标志的那些块。 如果块通过擦除验证，则块擦除标志被复位。 在擦除验证操作之后，仅具有设置块擦除标志的块被重新擦除。 为了支持这种操作，该电路还包括一次仅擦除存储器阵列的能力。