公开(公告)号：US06885529B2

公开(公告)日：2005-04-26

申请号：US09942785

申请日：2001-08-31

申请人： Ming-Dou Ker ,  Hun-Hsien Chang ,  Wen-Tai Wang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang ,  Wen-Tai Wang

IPC分类号： H01L23/60 ,  H01L27/02 ,  H02H3/22 ,  H02H9/00

CPC分类号： H01L27/0251

摘要： An object of the present invention is to provide a charged-device model (CDM) electrostatic discharge (ESD) protection circuit for an integrated circuit (IC). The ESD protection circuit comprises an ESD clamp device and a functional component. The ESD clamp device is coupled to a pad and a substrate having a first conductivity type. Under normal power operation, the ESD clamp device is closed. The functional component is formed on the substrate and coupled to the pad. The functional component has a first well having the first conductivity type and an isolating region having a second conductivity type for isolating the first well from the substrate. Under normal power operation, the functional component transmits signals between the IC and an external linkage. During an CDM ESD event, the CDM charges accumulated in the substrate are discharged via the ESD clamp circuit. Hence, the functional component is protected.

摘要翻译： 本发明的目的是提供一种用于集成电路（IC）的充电装置模型（CDM）静电放电（ESD）保护电路。 ESD保护电路包括ESD钳位装置和功能部件。 ESD钳位装置耦合到具有第一导电类型的焊盘和衬底。 在正常的电源操作下，ESD钳位装置关闭。 功能部件形成在基板上并且耦合到焊盘。 功能部件具有第一导电类型的第一阱和具有第二导电类型的隔离区，用于将第一阱与衬底隔离。 在正常功率操作下，功能组件在IC和外部连接之间传输信号。 在CDM ESD事件期间，积累在衬底中的CDM电荷通过ESD钳位电路放电。 因此，功能组件受到保护。

公开(公告)号：US06249410B1

公开(公告)日：2001-06-19

申请号：US09378948

申请日：1999-08-23

申请人： Ming-Dou Ker ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang

IPC分类号： H02H322

CPC分类号： H02H9/046 ,  H01L27/0251 ,  H01L27/0266

摘要： An ESD protection circuit is connected to an integrated circuit to dissipate an electrostatic charge from an ESD source placed in contact with two terminals of the integrated circuit to prevent damage to the integrated circuits. The ESD protection circuit has a ESD shunting circuit for shunting the electrostatic charge from integrated circuit. The ESD shunting circuit has a first port connected to one terminal of the integrated circuit, a second port connected to another terminal of the integrated circuit, and a third port. The ESD protection circuit additionally has an ESD detection circuit. The ESD detection circuit has a first input port connected to the one terminal of the integrated circuit, a second input port connected to the other terminal of the integrated circuit, and an output port connected to the third port of the ESD shunting circuit. When the ESD detection circuit detects the presence of the electrostatic charge from the ESD source, the ESD detection circuit generates an excess voltage at the third port that will damage the ESD shunting circuit. Finally The ESD protection circuit has a voltage clamping circuit connected between the third port of the ESD shunting circuit and one of the terminals of the integrated circuit to prevent the generation of the excess voltage at the third port of the ESD shunting circuit.

摘要翻译： ESD保护电路连接到集成电路以从与集成电路的两个端子接触的ESD源消散静电电荷，以防止对集成电路的损坏。 ESD保护电路具有用于从集成电路分流静电电荷的ESD分流电路。 ESD分流电路具有连接到集成电路的一个端子的第一端口，连接到集成电路的另一端子的第二端口和第三端口。 ESD保护电路还具有ESD检测电路。 ESD检测电路具有连接到集成电路的一个端子的第一输入端口，连接到集成电路的另一个端子的第二输入端口和连接到ESD分流电路的第三端口的输出端口。 当ESD检测电路检测到来自ESD源的静电电荷的存在时，ESD检测电路在第三端口产生将损坏ESD分流电路的过电压。 最后，ESD保护电路具有连接在ESD分流电路的第三端口与集成电路的一个端子之间的电压钳位电路，以防止在ESD分流电路的第三端口处产生过电压。

公开(公告)号：US6144542A

公开(公告)日：2000-11-07

申请号：US210954

申请日：1998-12-15

申请人： Ming-Dou Ker ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang

IPC分类号： H01L27/02 ,  H02H3/22

CPC分类号： H01L27/0292 ,  H01L27/0251

摘要： In this invention, a new whole-chip ESD protection scheme with the ESD buses has been proposed to solve the ESD protection issue of the CMOS IC having a large number of separated power lines. Multiple ESD buses, which are formed by the wide metal lines, have been added into the CMOS IC having a large number of separated power lines. The bi-directional ESD-connection cells are connected between the separated power lines and the ESD buses, but not between the separated power lines. The ESD current on the CMOS IC with more separated power lines are all conducted into the ESD buses, therefore the ESD current can be conducted by the ESD buses away from the internal circuits and quickly discharged through the designed ESD protection devices to ground. By using this new whole-chip ESD protection scheme with the ESD buses, the CMOS IC having more separated power lines can be still safely protected against ESD damages.

摘要翻译： 在本发明中，已经提出了具有ESD总线的新的全芯片ESD保护方案来解决具有大量分离电力线的CMOS IC的ESD保护问题。 由宽金属线形成的多个ESD总线已经被添加到具有大量分离电力线的CMOS IC中。 双向ESD连接单元连接在分离的电源线和ESD总线之间，而不是分离的电源线之间。 具有更多分离电源线的CMOS IC上的ESD电流都被导入ESD总线，因此ESD电流可以由ESD总线远离内部电路进行，并通过设计的ESD保护器件快速放电到地。 通过使用这种新的全芯片ESD保护方案与ESD总线，具有更多分离电源线的CMOS IC可以安全地防止ESD损坏。

公开(公告)号：US6011681A

公开(公告)日：2000-01-04

申请号：US140385

申请日：1998-08-26

申请人： Ming-Dou Ker ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang

IPC分类号： H01L27/02 ,  H02H3/22

CPC分类号： H01L27/0262 ,  H01L27/0251

摘要： CMOS VLSI chips with pin counts greater than 100 often have multiple power pins to supply sufficient current for circuit operations. In mixed voltage ICs there are separated power pins with different power supplies for specified power operations, and in these ICs the power supplies for the digital and analog circuits are often separated due to noise considerations. In such ICs with separated power pins, the interface circuits between the circuits with different power pins are vulnerable to ESD (electrostatic discharge) stress. Even though there are suitable ESD protection circuits around the input and output pins of the IC, unexpected ESD damage still happens to the interface circuits between the circuits with different power pins, so that a whole-chip ESD protection arrangement using bi-directional SCRs is provided to protect the CMOS ICs against ESD damage. The bi-directional SCRs are placed between the separated power lines of the CMOS IC to provide ESD current discharging paths between the separated power lines. Thus, the vulnerable internal circuits and interface circuits between the different power pins are rendered remote from the ESD damage. The present ESD protection arrangement can be applied to chips having multiple or mixed-voltage power pins.

摘要翻译： 引脚数大于100的CMOS VLSI芯片通常具有多个电源引脚，为电路操作提供足够的电流。 在混合电压IC中，具有用于指定功率操作的不同电源的分离的电源引脚，并且在这些IC中，由于噪声考虑，数字和模拟电路的电源通常是分离的。 在具有分离电源引脚的这种IC中，具有不同电源引脚的电路之间的接口电路易受ESD（静电放电）应力的影响。 即使在IC的输入和输出引脚周围有合适的ESD保护电路，但是在具有不同电源引脚的电路之间的接口电路仍然发生意外的ESD损坏，因此使用双向SCR的全芯片ESD保护装置是 用于保护CMOS IC免受ESD损坏。 将双向SCR放置在CMOS IC的分离的电源线之间，以提供分离的电力线之间的ESD电流放电路径。 因此，不同电源引脚之间的易损内部电路和接口电路远离ESD损坏。 本ESD保护装置可以应用于具有多个或混合电压电源引脚的芯片。

公开(公告)号：US5959820A

公开(公告)日：1999-09-28

申请号：US64894

申请日：1998-04-23

申请人： Ming-Dou Ker ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang

IPC分类号： H01L27/02 ,  H02H3/22

CPC分类号： H01L27/0248

摘要： The cascode LVTSCR includes two or more SCRs (silicon controlled rectifiers). Each SCR has an anode, a control gate, and a cathode. The SCRs are cascoded in series by coupling the control gates of same type SCRs in common and coupling the cathode of one SCR to the anode of next SCR in series. The holding voltage of the cascode LVTSCR can be designed to be greater than VDD voltage level of the IC. Therefore, the cascode LVTSCR has no latchup problem in the CMOS IC's. The electrostatic discharge (ESD) protection circuit in the present invention includes a cascode LVTSCR (low-voltage triggering silicon controlled rectifier) with an anode and a cathode coupled between power supplies, and a detecting circuit coupled between the power supplies for detecting an electrostatic charge to trigger the control gates of the cascode LVTSCR for dissipating the electrostatic discharge. The ESD protection circuit including the cascode LVTSCR can sustain high ESD stress but without causing the latchup problem in the CMOS IC's.

摘要翻译： 级联LVTSCR包括两个或更多个SCR（可控硅整流器）。 每个SCR具有阳极，控制栅极和阴极。 通过将相同类型的SCR的控制栅极共同连接并将一个SCR的阴极串联连接到下一个SCR的阳极，SCR串联。 级联LVTSCR的保持电压可以设计为大于IC的VDD电压电平。 因此，串联LVTSCR在CMOS IC中没有闭锁问题。 本发明中的静电放电（ESD）保护电路包括在电源之间连接有阳极和阴极的共源共栅LVTSCR（低电压触发可控硅整流器）和耦合在用于检测静电电荷的电源之间的检测电路 以触​​发级联LVTSCR的控制栅极用于消散静电放电。 包括共源共栅LVTSCR的ESD保护电路可以承受高ESD应力，但不会导致CMOS IC的闭锁问题。

公开(公告)号：US5576557A

公开(公告)日：1996-11-19

申请号：US422225

申请日：1995-04-14

申请人： Ming-Dou Ker ,  Chung-Yu Wu ,  Hun-Hsien Chang ,  Chung-Yuan Lee ,  Joe Ko

发明人： Ming-Dou Ker ,  Chung-Yu Wu ,  Hun-Hsien Chang ,  Chung-Yuan Lee ,  Joe Ko

IPC分类号： H01L27/02 ,  H01L29/74

CPC分类号： H01L27/0259 ,  H01L27/0251

摘要： An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR. The cathode and cathode gate of the second SCR are connected to the second power terminals. The anode of the second SCR is connected to its associated I/O buffering pads. The anode gate of the second SCR is connected to the first power terminal. The ESD circuit also comprises an NMOS transistor having drain, source, gate, and bulk terminals. The NMOS transistor's gate, source and bulk terminals are connected to the second power terminals. The NMOS transistor's drain terminal is connected to the anode gate of the second SCR.

摘要翻译： 公开了一种用于保护半导体集成电路（IC）器件的静电放电（ESD）电路。 一个ESD电路位于连接到一个引脚和IC的内部电路的每个I / O缓冲焊盘之间。 ESD电路连接到两个电源端子。 ESD电路包括第一和第二低电压触发SCR（LVTSCR），每个具有阳极，阴极，阳极栅极和阴极栅极。 第一SCR的阳极和阳极栅极连接到第一电源端子，第一SCR的阴极连接到其I / O缓冲焊盘，第一SCR的阴极栅极连接到第二电源端子。 ESD电路还包括具有漏极，源极，栅极和体积端子的PMOS晶体管。 PMOS晶体管的栅极，源极和体积端子连接到第一电源端子，PMOS晶体管漏极端子连接到第一SCR的阴极栅极。 第二SCR的阴极和阴极栅极连接到第二电源端子。 第二SCR的阳极连接到其相关的I / O缓冲垫。 第二SCR的阳极栅极连接到第一电源端子。 ESD电路还包括具有漏极，源极，栅极和体积端子的NMOS晶体管。 NMOS晶体管的栅极，源极和体积端子连接到第二个电源端子。 NMOS晶体管的漏极端子连接到第二SCR的阳极栅极。

公开(公告)号：US20090231765A1

公开(公告)日：2009-09-17

申请号：US12047356

申请日：2008-03-13

申请人： Ming-Dou Ker ,  Cheng-Cheng Yen ,  Chi-Sheng Liao ,  Tung-Yang Chen

发明人： Ming-Dou Ker ,  Cheng-Cheng Yen ,  Chi-Sheng Liao ,  Tung-Yang Chen

IPC分类号： H02H9/04

CPC分类号： G01R31/002 ,  G01R19/10

摘要： A digital converter including a first adjustment unit and a first transient detection unit. The first adjustment unit adjusts amplitude of an electrostatic discharge (ESD) pulse to generate a first adjustment signal when an ESD event occurs in a first power line and a second power line is at a complementary level. The first transient detection unit generates a first digital code according to the first adjustment signal.

摘要翻译： 一种数字转换器，包括第一调整单元和第一瞬态检测单元。 当在第一电力线中发生ESD事件并且第二电力线处于互补电平时，第一调整单元调节静电放电（ESD）脉冲的幅度以产生第一调整信号。 第一瞬态检测单元根据第一调整信号产生第一数字码。

公开(公告)号：US20090086392A1

公开(公告)日：2009-04-02

申请号：US12018224

申请日：2008-01-23

申请人： Ming-Dou Ker ,  Cheng-Cheng Yen ,  Tung-Yang Chen

发明人： Ming-Dou Ker ,  Cheng-Cheng Yen ,  Tung-Yang Chen

IPC分类号： H02H9/00

CPC分类号： H02H9/046

摘要： An ESD protection circuit including a discharge device, a first detection circuit, and a second detection circuit. The discharge device provides a discharge path between a first power rail and a second power rail when the discharge device is activated. The discharge device stops providing the discharge path when the discharge device is de-activated. The first detection circuit is coupled between the first and the second power rails. The first detection circuit activates the discharge device when an ESD event occurs in the first power rail. The second detection circuit de-activates the discharge device when the ESD event does not occur in the first power rail.

摘要翻译： 一种包括放电装置，第一检测电路和第二检测电路的ESD保护电路。 当排出装置被激活时，排放装置提供在第一动力轨道和第二动力轨道之间的排放路径。 当放电装置被去激活时，放电装置停止提供放电路径。 第一检测电路耦合在第一和第二电源轨之间。 当在第一电力轨道中发生ESD事件时，第一检测电路激活放电装置。 当在第一电力轨上没有发生ESD事件时，第二检测电路解除激活放电装置。

公开(公告)号：US07009826B2

公开(公告)日：2006-03-07

申请号：US11194021

申请日：2005-07-28

申请人： Ming-Dou Ker ,  Cheng-Ming Lee ,  Tung-Yang Chen

发明人： Ming-Dou Ker ,  Cheng-Ming Lee ,  Tung-Yang Chen

IPC分类号： H02H9/00

CPC分类号： H01L27/0288 ,  H01L23/60 ,  H01L24/06 ,  H01L27/0255 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

摘要： An ESD protection circuit design incorporating a single, or a plurality of, parallel inductor and capacitor, also known as LC tank(s), to avoid power loss by parasitic capacitance in ESD circuits. The first design described incorporates a LC tank structure. The second includes two LC tank structures. These structures can be expanded to form ESD protection circuit structures stacked with n-stages LC tanks. The last design described is ESD protection circuits formed by stacking the first design. These designs can avoid power gain loss from parasitic capacitance of ESD, because the parameters of LC tank can be designed to resonant at a desired operating frequency. Each of these designs can be altered slightly to create variant designs with equal identical ESD protection capabilities.

摘要翻译： 包括单个或多个并联电感器和电容器（也称为LC箱）的ESD保护电路设计，以避免ESD电路中的寄生电容的功率损耗。 所描述的第一个设计包括一个LC液箱结构。 第二个包括两个LC坦克结构。 这些结构可以扩展，形成堆积在n级液晶盒中的ESD保护电路结构。 所描述的最后一个设计是通过堆叠第一设计形成的ESD保护电路。 这些设计可以避免由ESD寄生电容引起的功率增益损失，因为LC槽的参数可以设计成在所需工作频率下谐振。 这些设计中的每一个都可以稍微修改，以创建具有相同ESD保护功能的变体设计。

公开(公告)号：US08829775B2

公开(公告)日：2014-09-09

申请号：US13464506

申请日：2012-05-04

申请人： Tung-Yang Chen ,  Ming-Dou Ker ,  Ryan Hsin-Chin Jiang

发明人： Tung-Yang Chen ,  Ming-Dou Ker ,  Ryan Hsin-Chin Jiang

IPC分类号： H01J1/88 ,  H01J19/42 ,  H01J1/00 ,  H01J1/18

CPC分类号： H01J9/02 ,  H01J17/066

摘要： The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.

摘要翻译： 本发明公开了一种基于半导体的平面微管放电器结构及其制造方法。 该方法包括以下步骤：在衬底上形成由间隙分开的两个图案化电极和布置在间隙中的至少一个分隔块; 在图案化电极和分离块上形成绝缘层，并将绝缘层填充到间隙中。 由此形成至少两个排出路径。 该方法可以在半导体结构中制造多个放电路径。 因此，本发明的结构具有非常高的可靠性和可重用性。