ISOLATION STRUCTURE, NON-VOLATILE MEMORY HAVING THE SAME, AND METHOD OF FABRICATING THE SAME
    11.
    发明申请
    ISOLATION STRUCTURE, NON-VOLATILE MEMORY HAVING THE SAME, AND METHOD OF FABRICATING THE SAME 有权
    隔离结构,具有该隔离结构的非易失性存储器及其制造方法

    公开(公告)号:US20120049269A1

    公开(公告)日:2012-03-01

    申请号:US13291374

    申请日:2011-11-08

    IPC分类号: H01L29/792 H01L29/06

    CPC分类号: H01L21/76229 H01L21/76205

    摘要: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.

    摘要翻译: 一种形成隔离结构的方法,包括:(a)提供具有凹部的基部; (b)在基座和凹槽中形成停止层; (c)在所述阻挡层上形成电介质材料,以允许所述凹部的其余部分填充所述电介质材料; (d)通过进行化学机械抛光(CMP)工艺在基底上去除电介质材料,直到一部分停止层被暴露以在凹槽中形成电介质层; 和(e)去除所述阻挡层的一部分,其中所述阻挡层的另一部分和填充在所述凹部中的所述电介质层构成所述隔离结构。

    Contact barrier layer deposition process
    12.
    发明授权
    Contact barrier layer deposition process 有权
    接触阻挡层沉积工艺

    公开(公告)号:US07846835B2

    公开(公告)日:2010-12-07

    申请号:US11950319

    申请日:2007-12-04

    IPC分类号: H01L21/4763

    摘要: A method for depositing a barrier layer onto a substrate is disclosed. A layer of titanium (Ti) is deposited onto the substrate using an ionized metal plasma (IMP) physical vapor deposition process. The IMP process includes: generating gaseous ions, accelerating the gaseous ions towards a titanium target, sputtering the titanium atoms from the titanium target with the gaseous ions, ionizing the titanium atoms using a plasma, and depositing the ionized titanium atoms onto the substrate to form the layer of Ti. A first layer of titanium nitride (TiN) is deposited onto the layer of Ti using a metal organic chemical vapor deposition (MOCVD) process. A second layer of TiN is deposited onto the first layer of TiN using a thermal chemical vapor deposition process. The newly completed barrier layer is annealed in the presence of nitrogen at a temperature of between about 500° C. to about 750° C.

    摘要翻译: 公开了一种在衬底上沉积阻挡层的方法。 使用电离金属等离子体(IMP)物理气相沉积工艺将一层钛(Ti)沉积到衬底上。 IMP过程包括:产生气体离子,将气态离子加速到钛靶,用钛离子溅射钛原子与气态离子,使用等离子体离子化钛原子,并将离子化的钛原子沉积到基底上形成 Ti层。 使用金属有机化学气相沉积(MOCVD)工艺将第一层氮化钛(TiN)沉积到Ti层上。 使用热化学气相沉积工艺将第二层TiN沉积到第一TiN层上。 将新完成的阻挡层在氮气存在下在约500℃至约750℃的温度下进行退火。

    Interconnection process
    13.
    发明申请
    Interconnection process 有权
    互连过程

    公开(公告)号:US20080299761A1

    公开(公告)日:2008-12-04

    申请号:US11806541

    申请日:2007-06-01

    IPC分类号: H01L21/4763

    摘要: An interconnection process is provided. The process includes the following steps. Firstly, a semiconductor base having at least a electrical conductive region is provided. Next, a dielectric layer with a contact hole is formed to cover the semiconductor base, wherein the contact hole exposes part of the electrical conductive region. Then, a thermal process is performed on the semiconductor base covered with the dielectric layer. Lastly, a conductive layer is formed on the dielectric layer, wherein the conductive layer is electrically connected to the electrical conductive region through the contact hole.

    摘要翻译: 提供互连过程。 该过程包括以下步骤。 首先,设置至少具有导电区域的半导体基板。 接下来,形成具有接触孔的电介质层以覆盖半导体基底,其中接触孔暴露部分导电区域。 然后,对覆盖有电介质层的半导体基板进行热处理。 最后,在电介质层上形成导电层,其中导电层通过接触孔与导电区电连接。

    Isolation structure, non-volatile memory having the same, and method of fabricating the same
    14.
    发明授权
    Isolation structure, non-volatile memory having the same, and method of fabricating the same 有权
    隔离结构,具有相同的非易失性存储器及其制造方法

    公开(公告)号:US08067292B2

    公开(公告)日:2011-11-29

    申请号:US12343633

    申请日:2008-12-24

    IPC分类号: H01L21/76

    CPC分类号: H01L21/76229 H01L21/76205

    摘要: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.

    摘要翻译: 一种形成隔离结构的方法,包括:(a)提供具有凹部的基部; (b)在基座和凹槽中形成停止层; (c)在所述阻挡层上形成电介质材料,以允许所述凹部的其余部分填充所述电介质材料; (d)通过进行化学机械抛光(CMP)工艺在基底上去除电介质材料,直到一部分停止层被暴露以在凹槽中形成电介质层; 和(e)去除所述阻挡层的一部分,其中所述阻挡层的另一部分和填充在所述凹部中的所述电介质层构成所述隔离结构。

    Method for manufacturing a semiconductor device
    15.
    发明申请
    Method for manufacturing a semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号:US20100038786A1

    公开(公告)日:2010-02-18

    申请号:US12228764

    申请日:2008-08-14

    IPC分类号: H01L23/48 H01L21/44

    摘要: A method for manufacturing a semiconductor device is disclosed. A semiconductor substrate such as bare silicon is provided, and a dielectric layer is formed over the semiconductor substrate. An opening is provided within the dielectric layer by removing a portion of the dielectric layer. A conformal first conductive layer is formed over the dielectric layer and the opening. A conformal second conductive layer is formed over the first conductive layer. A conformal barrier layer is formed over the second conductive layer.

    摘要翻译: 公开了一种制造半导体器件的方法。 提供诸如裸硅的半导体衬底,并且在半导体衬底上形成电介质层。 通过去除介电层的一部分,在电介质层内提供开口。 在电介质层和开口上形成共形的第一导电层。 在第一导电层上形成共形的第二导电层。 在第二导电层上形成共形势垒层。

    ISOLATION STRUCTURE, NON-VOLATILE MEMORY HAVING THE SAME, AND METHOD OF FABRICATING THE SAME
    16.
    发明申请
    ISOLATION STRUCTURE, NON-VOLATILE MEMORY HAVING THE SAME, AND METHOD OF FABRICATING THE SAME 有权
    隔离结构,具有该隔离结构的非易失性存储器及其制造方法

    公开(公告)号:US20090184343A1

    公开(公告)日:2009-07-23

    申请号:US12343633

    申请日:2008-12-24

    CPC分类号: H01L21/76229 H01L21/76205

    摘要: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.

    摘要翻译: 一种形成隔离结构的方法,包括:(a)提供具有凹部的基部; (b)在基座和凹槽中形成停止层; (c)在所述阻挡层上形成电介质材料,以允许所述凹部的其余部分填充所述电介质材料; (d)通过进行化学机械抛光(CMP)工艺在基底上去除电介质材料,直到一部分停止层被暴露以在凹槽中形成电介质层; 和(e)去除所述阻挡层的一部分,其中所述阻挡层的另一部分和填充在所述凹部中的所述电介质层构成所述隔离结构。

    Metallization process
    17.
    发明申请
    Metallization process 审中-公开
    金属化过程

    公开(公告)号:US20090081859A1

    公开(公告)日:2009-03-26

    申请号:US11902228

    申请日:2007-09-20

    IPC分类号: H01L21/425

    摘要: A metallization process is provided. The metallization process comprises the following steps. First, a semiconductor base having at least a silicon-containing conductive region is provided. Afterwards, nitrogen ions are implanted into the silicon-containing conductive region. Next, a first thermal process is performed on the semiconductor base for repairing the surface of the semiconductor base. Then, a metal layer is formed on the surface of the semiconductor base and the metal layer covers the silicon-containing conductive region. Lastly, a second thermal process is performed on the semiconductor base covered with the metal layer so as to form a metal silicide layer on the silicon-containing conductive region.

    摘要翻译: 提供金属化工艺。 金属化处理包括以下步骤。 首先,提供至少具有含硅导电区域的半导体基底。 之后,将氮离子注入含硅导电区域。 接下来,对半导体基板进行第一热处理,以修复半导体基底的表面。 然后,在半导体基底的表面上形成金属层,并且金属层覆盖含硅导电区域。 最后,在覆盖有金属层的半导体基底上进行第二热处理,以在含硅导电区域上形成金属硅化物层。

    CONTACT BARRIER LAYER DEPOSITION PROCESS
    18.
    发明申请
    CONTACT BARRIER LAYER DEPOSITION PROCESS 审中-公开
    联系障碍层沉积过程

    公开(公告)号:US20080132060A1

    公开(公告)日:2008-06-05

    申请号:US11565355

    申请日:2006-11-30

    IPC分类号: H01L21/44

    摘要: A method for depositing a barrier layer onto a substrate is disclosed. A layer of titanium (Ti) is deposited onto the substrate using an ionized metal plasma physical vapor deposition process, wherein the layer of Ti has a thickness of between about 10 angstroms (Å) and about 1000 Å. A first layer of titanium nitride (TiN) is deposited onto the layer of Ti using a metal organic chemical vapor deposition process, wherein the first layer of TiN has a thickness of between about 1 Å and about 100 Å. A second layer of TiN is deposited onto the first layer of TiN using a thermal chemical vapor deposition process, wherein the second layer of TiN has a thickness of between about 10 Å and about 750 Å.

    摘要翻译: 公开了一种在衬底上沉积阻挡层的方法。 使用离子化的金属等离子体物理气相沉积工艺将一层钛(Ti)沉积到衬底上,其中Ti层的厚度介于约10埃至约1000埃之间。 使用金属有机化学气相沉积工艺将第一层氮化钛(TiN)沉积到Ti层上,其中TiN的第一层具有在约和之间的厚度。 使用热化学气相沉积工艺将第二TiN层沉积到第一TiN层上,其中TiN的第二层具有介于约和之间的厚度。

    Semiconductor device having plural conductive layers disposed within dielectric layer
    19.
    发明授权
    Semiconductor device having plural conductive layers disposed within dielectric layer 有权
    具有设置在电介质层内的多个导电层的半导体器件

    公开(公告)号:US08519541B2

    公开(公告)日:2013-08-27

    申请号:US12228764

    申请日:2008-08-14

    IPC分类号: H01L23/532

    摘要: A method for manufacturing a semiconductor device is disclosed. A semiconductor substrate such as bare silicon is provided, and a dielectric layer is formed over the semiconductor substrate. An opening is provided within the dielectric layer by removing a portion of the dielectric layer. A conformal first conductive layer is formed over the dielectric layer and the opening. A conformal second conductive layer is formed over the first conductive layer. A conformal barrier layer is formed over the second conductive layer.

    摘要翻译: 公开了一种制造半导体器件的方法。 提供诸如裸硅的半导体衬底,并且在半导体衬底上形成电介质层。 通过去除介电层的一部分,在电介质层内提供开口。 在电介质层和开口上形成共形的第一导电层。 在第一导电层上形成共形的第二导电层。 在第二导电层上形成共形势垒层。

    CONTACT BARRIER LAYER DEPOSITION PROCESS
    20.
    发明申请
    CONTACT BARRIER LAYER DEPOSITION PROCESS 审中-公开
    联系障碍层沉积过程

    公开(公告)号:US20110056432A1

    公开(公告)日:2011-03-10

    申请号:US12945666

    申请日:2010-11-12

    IPC分类号: H01L21/4763

    摘要: A method for depositing a barrier layer onto a substrate is disclosed. A layer of titanium (Ti) is deposited onto the substrate using an ionized metal plasma (IMP) physical vapor deposition process. The IMP process includes: generating gaseous ions, accelerating the gaseous ions towards a titanium target, sputtering the titanium atoms from the titanium target with the gaseous ions, ionizing the titanium atoms using a plasma, and depositing the ionized titanium atoms onto the substrate to form the layer of Ti. A first layer of titanium nitride (TiN) is deposited onto the layer of Ti using a metal organic chemical vapor deposition (MOCVD) process. A second layer of TiN is deposited onto the first layer of TiN using a thermal chemical vapor deposition process. The newly completed barrier layer is annealed in the presence of nitrogen at a temperature of between about 500° C. to about 750° C.

    摘要翻译: 公开了一种在衬底上沉积阻挡层的方法。 使用电离金属等离子体(IMP)物理气相沉积工艺将一层钛(Ti)沉积到衬底上。 IMP过程包括:产生气体离子,将气态离子加速到钛靶,用钛离子溅射钛原子与气态离子,使用等离子体离子化钛原子,并将离子化的钛原子沉积到基底上形成 Ti层。 使用金属有机化学气相沉积(MOCVD)工艺将第一层氮化钛(TiN)沉积到Ti层上。 使用热化学气相沉积工艺将第二层TiN沉积到第一TiN层上。 将新完成的阻挡层在氮气存在下在约500℃至约750℃的温度下进行退火。