SLEEP CURRENT ADJUSTING CIRCUIT OF SYSTEM ON CHIP
    11.
    发明申请
    SLEEP CURRENT ADJUSTING CIRCUIT OF SYSTEM ON CHIP 审中-公开
    休眠电流调节系统芯片电路

    公开(公告)号:US20080278139A1

    公开(公告)日:2008-11-13

    申请号:US12105966

    申请日:2008-04-18

    IPC分类号: H02M3/156

    CPC分类号: G11C5/14 G11C5/148

    摘要: There is provided a sleep current adjusting circuit of a system on chip including: a regulator supplying a turn-on voltage and a normal current when a mode selection signal is a normal mode signal, and a turn-off voltage when the mode selection signal is a sleep mode signal; a switching device turned on by the turn-on voltage of the regulator to supply the normal current from the regulator to a main circuit part and a sleep operation circuit part, respectively, and turned off by the turn-off voltage of the regulator to block the normal current from being supplied to the main circuit part and supply the sleep current to the sleep operation circuit part; and a current limit device limiting an operating current flowing in response to the operating voltage and supplying the sleep current to the sleep operation circuit part.

    摘要翻译: 提供了一种片上系统的睡眠电流调节电路,包括:当模式选择信号是正常模式信号时,提供接通电压和正常电流的调节器,以及当模式选择信号为 睡眠模式信号; 开关装置由调节器的导通电压导通,以分别将调节器的正常电流提供给主电路部分和睡眠操作电路部分,并通过调节器的截止电压将其截止以阻止 正常电流被提供给主电路部分并将睡眠电流提供给睡眠操作电路部分; 以及电流限制装置,其限制响应于所述工作电压流动的工作电流并将睡眠电流提供给所述睡眠操作电路部分。

    DUAL MODE WPAN TRANSCEIVER
    12.
    发明申请
    DUAL MODE WPAN TRANSCEIVER 审中-公开
    双模WPAN收发器

    公开(公告)号:US20080137570A1

    公开(公告)日:2008-06-12

    申请号:US11951040

    申请日:2007-12-05

    IPC分类号: H04B7/00 H04L27/00

    摘要: There is provided a dual mode WPAN transceiver including a dual mode WPAN transmitter and a dual mode WPAN receiver. In the dual mode WPAN transceiver, the dual mode WPAN transmitter includes a low-speed spreading transmission block spreading low bit-rate data corresponding to a low data rate in low data rate mode, and a high-speed encoding transmission block encoding high bit-rate data corresponding to a high data rate in high data rate mode, and the dual mode WPAN receiver includes an A/D block converting analog I and Q signals into digital I and Q signals, a differential block obtaining a phase difference between the digital I and Q signals from the A/D unit and complex signals adjacent thereto to offset phase errors of the digital I and Q signals, a low-speed despreading reception unit despreading the digital I and Q signals differentiated by the differential block to detect low bit-rate data in low data rate mode, and a high-speed decoding reception unit decoding the digital I and Q signals differentiated by the differential block to detect high bit-rate data.

    摘要翻译: 提供了一种双模WPAN收发器,包括双模WPAN发送器和双模WPAN接收器。 在双模WPAN收发器中,双模WPAN发送器包括一个低速扩展传输块,它以低数据速率模式扩展对应于低数据速率的低比特率数据,以及一个高位编码传输块, 速率数据对应于高数据速率模式下的高数据速率,双模WPAN接收机包括将模拟I和Q信号转换成数字I和Q信号的A / D块,差分块获得数字I 和来自A / D单元的Q信号和与其相邻的复信号以消除数字I和Q信号的相位误差;低速解扩接收单元解扩由差分块区分的数字I和Q信号,以检测低位 - 低数据速率模式的速率数据,以及对由差分块区分的数字I和Q信号进行解码以检测高比特率数据的高速解码接收单元。

    DATA TRANSMISSION METHOD INDICATING DATA PENDING IN ZIGBEE NETWORK
    13.
    发明申请
    DATA TRANSMISSION METHOD INDICATING DATA PENDING IN ZIGBEE NETWORK 审中-公开
    数据传输方法表明ZigBee网络中的数据丢失

    公开(公告)号:US20080075005A1

    公开(公告)日:2008-03-27

    申请号:US11860324

    申请日:2007-09-24

    IPC分类号: G08C15/00

    CPC分类号: H04W28/06 H04W48/12 H04W84/18

    摘要: A data transmission method indicating data pending in a ZigBee network is provided, wherein the data transmission method is used to shorten a delay time for data transmission by setting a certain bit to indicate data pending in the ZigBee network to a ZigBee device, the certain bit indicating data pending to an acknowledge frame for acknowledging a data frame from the ZigBee device. The data transmission method according to the present invention includes broadcasting beacons so as to allow the ZigBee coordinator to maintain the connection of the ZigBee network; downloading a data frame from an assigned ZigBee device transmitting the data frame by receiving the beacons; and transmitting an acknowledge frame including a data pending bit indicating data pending to the assigned ZigBee device.

    摘要翻译: 提供了一种指示ZigBee网络中待处理数据的数据传输方法,其中数据传输方法用于通过设置某一位来缩短数据传输的延迟时间,以将ZigBee网络中的待处理数据指示给ZigBee设备,该特定位 将待处理的数据指示到用于确认来自ZigBee设备的数据帧的确认帧。 根据本发明的数据传输方法包括广播信标,以便允许ZigBee协调器维持ZigBee网络的连接; 从分配的ZigBee设备下载数据帧,通过接收信标发送数据帧; 以及发送包括指示数据待处理的数据等待位的确认帧到所分配的ZigBee设备。

    Apparatus and system for viewing 3D image
    14.
    发明授权
    Apparatus and system for viewing 3D image 有权
    用于观看3D图像的装置和系统

    公开(公告)号:US08441413B2

    公开(公告)日:2013-05-14

    申请号:US12827026

    申请日:2010-06-30

    IPC分类号: G09G5/00

    摘要: An apparatus and a system for viewing a 3D image including a synchronization signal receiver for receiving 3D image synchronization signal; a 3D control signal generator for generating left-eye glass control signal and a right-eye glass control signal in accordance with the synchronization signal received; a left-eye glass that opens or intercepts light transmitted to the left-eye glass; a right-eye glass that opens or intercepts light transmitted to the right-eye glass; a central processor that controls operation of the 3D control signal generator and transmits the synchronization signal to the 3D control signal generator; and a power controller that connects or intercepts power supplied to the synchronization signal receiver and the central processor. The power consumption of the apparatus is minimized by supplying power to the synchronization signal receiver and the central processor at a time when the synchronization signal is received and power is intercepted during the rest period.

    摘要翻译: 一种用于观看包括用于接收3D图像同步信号的同步信号接收器的3D图像的装置和系统; 用于根据所接收的同步信号产生左眼玻璃控制信号和右眼玻璃控制信号的3D控制信号发生器; 打开或拦截透射到左眼玻璃的光的左眼玻璃; 打开或拦截透射到右眼玻璃的光的右眼玻璃; 控制3D控制信号发生器的操作并将同步信号发送到3D控制信号发生器的中央处理器; 以及功率控制器,其连接或截取提供给同步信号接收器和中央处理器的功率。 在同步信号被接收并且在休息期间被截取电力的时刻,通过向同步信号接收机和中央处理器供电来使设备的功耗最小化。

    DIGITAL AMPLITUDE MODULATOR AND POLAR TRANSMITTER USING THEREOF
    16.
    发明申请
    DIGITAL AMPLITUDE MODULATOR AND POLAR TRANSMITTER USING THEREOF 审中-公开
    数字振幅调制器及其使用的极性发射器

    公开(公告)号:US20110280334A1

    公开(公告)日:2011-11-17

    申请号:US12859800

    申请日:2010-08-20

    IPC分类号: H04L27/00 H03C1/02

    摘要: The present invention provides a digital amplitude modulator and polar transmitter using the same. The polar transmitter includes: a polar converter for converting an input signal into an amplitude information signal and a phase information signal, and outputting the converted amplitude and phase information signal; a sigma-delta modulator for receiving a fractional part of the amplitude information signal, and generating a correcting value for an integer part of the amplitude information signal; a phase-modulator for upward-modulating the phase information signal outputted from the polar converter, and outputting carrier waves including the upward-modulated phase information signal; and a digital power amplifier for generating an output signal whose amplitude corresponds to the integer part of the amplitude information signal which is subjected to correction by the correcting value, and outputting combining the output signal with an output value of the phase-modulator to output the combined signal.

    摘要翻译: 本发明提供一种数字振幅调制器和使用该调幅器的极化发射机。 极性发射机包括:极化转换器,用于将输入信号转换为振幅信息信号和相位信息信号,并输出转换的幅度和相位信息信号; 一个Σ-Δ调制器,用于接收幅度信息信号的分数部分,并产生一个幅度信息信号整数部分的校正值; 相位调制器,用于对从极化转换器输出的相位信息信号进行向上调制,并输出包括向上调制相位信息信号的载波; 以及数字功率放大器,用于产生其幅度对应于通过校正值进行校正的振幅信息信号的整数部分的输出信号,并且输出将输出信号与相位调制器的输出值相组合以输出 组合信号。

    Timing estimator in OQPSK demodulator
    17.
    发明授权
    Timing estimator in OQPSK demodulator 有权
    OQPSK解调器中的定时估计器

    公开(公告)号:US07792216B2

    公开(公告)日:2010-09-07

    申请号:US11549025

    申请日:2006-10-12

    IPC分类号: H03K9/00 H04L27/00

    摘要: A timing estimator of an OQPSK demodulator is provided. In the timing estimator, an A/D converter converts an analog reception signal into a digital reception signal. A differential circuit section delays the digital reception signal from the A/D converter by a preset time and obtains a phase difference between a conjugate complex number signal of the delayed digital reception signal and the digital reception signal to offset a frequency error contained in the digital reception signal. A correlation operation section performs a correlation operation between a reference symbol differentiated in the same way as a differentiation of the differential circuit section and the reception signal to obtain each correlation value. A coherent detector detects a coherent point on the basis of the correlation value from the correlation operation section.

    摘要翻译: 提供OQPSK解调器的定时估计器。 在定时估计器中,A / D转换器将模拟接收信号转换为数字接收信号。 差分电路部分将来自A / D转换器的数字接收信号延迟预设时间,并且获得延迟的数字接收信号的共轭复数信号与数字接收信号之间的相位差,以抵消包含在数字 接收信号。 相关运算部分以与差分电路部分的微分和接收信号相同的方式执行区分的参考符号之间的相关运算,以获得每个相关值。 相干检测器根据相关运算部分的相关值检测相干点。

    Pad controlling apparatus
    19.
    发明授权
    Pad controlling apparatus 失效
    垫控制装置

    公开(公告)号:US08564360B2

    公开(公告)日:2013-10-22

    申请号:US13440497

    申请日:2012-04-05

    IPC分类号: G05F1/10

    CPC分类号: G06F1/32

    摘要: Disclosed herein is a pad controlling apparatus controlling current and voltage applied to a pad, the pad controlling apparatus including: a voltage drop unit dropping the voltage applied to the pad; a switching unit connected in parallel with the voltage drop unit; and a control unit comparing a level of the dropped voltage and first reference voltage with each other and turning on the switching unit on when the level of the dropped voltage is larger than the first reference voltage. According to the present invention, even though interrupt occurs from the outside, a chip may be normally operated.

    摘要翻译: 这里公开了一种控制施加到焊盘的电流和电压的焊盘控制装置,焊盘控制装置包括:降压单元,降低施加到焊盘的电压; 开关单元,与所述电压降单元并联连接; 以及控制单元,其将所述下降电压和所述第一参考电压的电平相互比较,并且在所述下降电压的电平大于所述第一参考电压时接通所述开关单元。 根据本发明,即使从外部发生中断,芯片也可以正常工作。

    POWER FACTOR CORRECTION APPARATUS, DC/DC CONVERTER, AND POWER SUPPLYING APPARATUS
    20.
    发明申请
    POWER FACTOR CORRECTION APPARATUS, DC/DC CONVERTER, AND POWER SUPPLYING APPARATUS 审中-公开
    功率因数校正装置,DC / DC转换器和电源设备

    公开(公告)号:US20130135910A1

    公开(公告)日:2013-05-30

    申请号:US13591580

    申请日:2012-08-22

    IPC分类号: G05F1/70 H02M7/06

    摘要: There are provided a power factor correction apparatus, a direct current/direct current (DC/DC) converter, and a power supplying apparatus, capable of preventing unstable feedback control due to a ripple component by controlling power switching based on a median value between a maximum value and a minimum value of a voltage level of the output power that is received as feedback. The power factor correction apparatus includes a power factor corrector switching input power and correcting a power factor thereof; and a controller detecting a voltage level of power factor-corrected power and controlling the switching of the power factor corrector, based on a median value between a maximum value and a minimum value of the voltage level of the power factor-corrected power detected for a predetermined period of time.

    摘要翻译: 提供了功率因数校正装置,直流/直流(DC / DC)转换器和供电装置,其能够通过基于中间值控制功率切换来防止由于纹波分量引起的不稳定的反馈控制 作为反馈接收的输出功率的电压电平的最大值和最小值。 功率因数校正装置包括功率因数校正器切换输入功率并校正其功率因数; 以及控制器,其基于所检测的功率因数校正功率的电压电平的最大值和最小值之间的中值,检测功率因数校正功率的电压电平并控制功率因数校正器的切换, 预定时间段。