公开(公告)号：US10347642B2

公开(公告)日：2019-07-09

申请号：US15856024

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Chien-Ting Ho ,  Shih-Fang Tzou ,  Fu-Che Lee

IPC: H01L21/76 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/78 ,  H01L21/28 ,  H01L27/108 ,  H01L21/02

Abstract: A manufacturing method of a semiconductor memory device is provided in the present invention. A cleaning treatment to a storage node contact on a semiconductor substrate is performed, and a metal silicide layer is formed after the cleaning treatment. A gate contact opening penetrating a capping layer of a transistor on the semiconductor substrate is formed after the step of forming the metal silicide layer for exposing a gate structure of the transistor. By the manufacturing method of the semiconductor memory device in the present invention, the gate structure of the transistor may be kept from being influenced and/or damaged by the cleaning treatment of the storage node contact, and the electrical performance of the transistor may be ensured accordingly.

公开(公告)号：US20190206982A1

公开(公告)日：2019-07-04

申请号：US16297733

申请日：2019-03-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Po-Chun Chen ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Wen-Chieh Lu ,  Chien-Ting Ho ,  Tsung-Ying Tsai ,  Kai-Ping Chen

IPC: H01L49/02 ,  H01L27/108 ,  H01L29/94

Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.

公开(公告)号：US10236294B2

公开(公告)日：2019-03-19

申请号：US15854827

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Ting Ho ,  Shih-Fang Tzou ,  Chun-Yuan Wu ,  Li-Wei Feng ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Tsung-Ying Tsai

IPC: H01L27/105 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3105

Abstract: The present invention proposes a method of manufacturing a semiconductor device, which includes the steps of providing a substrate with a memory region and a logic region, forming bit lines and logic gates respectively in the memory region and the logic region, wherein storage node regions are defined between bit lines, forming a first low-K dielectric layer on sidewalls of bit lines, forming a doped silicon layer in the storage node regions between bit lines, wherein the top surface of doped silicon layer is lower than the top surface of bit line, forming a second low-K dielectric layer on sidewalls of storage node regions, and filling up storage node regions with metal plugs.

公开(公告)号：US20180277546A1

公开(公告)日：2018-09-27

申请号：US15915026

申请日：2018-03-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/10894 ,  H01L21/76224 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10897 ,  H01L29/0649

Abstract: A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a plurality of bit lines, a gate, a spacer layer and a first spacer. The substrate has a memory cell region and a periphery region, the a plurality of bit lines are disposed on the substrate, within the memory cell region, and the gate is disposed on the substrate, within the periphery. The spacer layer covers the bit lines and a sidewall of the gate. The first spacer is disposed at two sides of the gate, covers on the spacer layer.

公开(公告)号：US10068907B1

公开(公告)日：2018-09-04

申请号：US15593338

申请日：2017-05-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tsung-Ying Tsai ,  Chien-Ting Ho ,  Ming-Te Wei ,  Li-Wei Feng ,  Ying-Chiao Wang

IPC: H01L23/528 ,  H01L27/108 ,  H01L29/06

Abstract: A dynamic random access memory (DRAM) includes a substrate, two buried word lines and a bit line contact. The substrate includes a first active area, wherein the first active area extends along a first direction. The buried word lines are disposed in the substrate and across the first active area, wherein the buried word lines extend along a second direction. The bit line contact is disposed on the substrate and overlaps the first active area between the two buried word lines, wherein the bit line contact is enclosed by a first side, a second side, a third side and a fourth side, and the first side is parallel to the third side along a third direction while the second side is parallel to the fourth side along a fourth direction, wherein the third direction is parallel to the first direction and the fourth direction is parallel to the second direction.

公开(公告)号：US20180190656A1

公开(公告)日：2018-07-05

申请号：US15854827

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Ting Ho ,  Shih-Fang Tzou ,  Chun-Yuan Wu ,  Li-Wei Feng ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Tsung-Ying Tsai

IPC: H01L27/105 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L27/1052 ,  H01L21/02532 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1085 ,  H01L27/10894 ,  H01L29/6653 ,  H01L29/6656

Abstract: The present invention proposes a method of manufacturing a semiconductor device, which includes the steps of providing a substrate with a memory region and a logic region, forming bit lines and logic gates respectively in the memory region and the logic region, wherein storage node regions are defined between bit lines, forming a first low-K dielectric layer on sidewalls of bit lines, forming a doped silicon layer in the storage node regions between bit lines, wherein the top surface of doped silicon layer is lower than the top surface of bit line, forming a second low-K dielectric layer on sidewalls of storage node regions, and filling up storage node regions with metal plugs.

公开(公告)号：US09960167B1

公开(公告)日：2018-05-01

申请号：US15678132

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Ting Ho ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Yu-Chieh Lin

IPC: H01L27/108 ,  H01L29/45 ,  H01L29/423

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10897

Abstract: A method for forming a semiconductor device includes providing a substrate having a plurality of memory cells formed therein; forming an insulating layer on the substrate; forming a plurality of openings in the insulating layer and exposing a portion of the memory cells; forming a conductive portion and a metal layer in the openings; removing a portion of the metal layer to form a plurality of first metal portions and a plurality of second metal portions that the first metal portion and the conductive portion form a first connecting structure, and the second metal portion and the conductive portion form a second connecting structure; forming a passivation layer on the first connecting structures; and forming a plurality of first storage nodes and dummy nodes on the substrate and the first storage nodes and the dummy nodes are electrically connected to the second connecting structures and the first connecting structures respectively.

公开(公告)号：US20180108563A1

公开(公告)日：2018-04-19

申请号：US15384940

申请日：2016-12-20

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chieh-Te Chen ,  Hsien-Shih Chu ,  Ming-Feng Kuo ,  Fu-Che Lee ,  Chien-Ting Ho ,  Chiung-Lin Hsu ,  Feng-Yi Chang ,  Yi-Wang Zhan ,  Li-Chiang Chen ,  Chien-Cheng Tsai ,  Chin-Hsin Chiu

IPC: H01L21/762 ,  H01L21/308

CPC classification number: H01L21/76224 ,  H01L21/3081 ,  H01L21/762

Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.

公开(公告)号：US11049863B2

公开(公告)日：2021-06-29

申请号：US15889182

申请日：2018-02-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Ting Ho ,  Ying-Chiao Wang ,  Yu-Ching Chen ,  Hui-Ling Chuang ,  Kuei-Hsuan Yu

IPC: H01L27/108

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

公开(公告)号：US10553591B2

公开(公告)日：2020-02-04

申请号：US16294934

申请日：2019-03-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/108

Abstract: A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.