公开(公告)号：US11882683B2

公开(公告)日：2024-01-23

申请号：US17561663

申请日：2021-12-23

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Chien-Ming Lu ,  Fu-Che Lee ,  Chien-Cheng Tsai ,  Chiu-Fang Hsu

IPC分类号： H10B12/00 ,  H01L21/311 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/3065

CPC分类号： H10B12/053 ,  H01L21/02164 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/0653 ,  H10B12/34 ,  H01L21/02238 ,  H10B12/488

摘要： A method of forming a semiconductor memory device, the semiconductor memory device includes a plurality of active areas, a shallow trench isolation, a plurality of trenches and a plurality of gates. The active areas are defined on a semiconductor substrate, and surrounded by the shallow trench isolation. The trenches are disposed in the semiconductor substrate, penetrating through the active areas and the shallow trench isolation, wherein each of the trenches includes a bottom surface and a saddle portion protruded therefrom in each active areas. The gates are disposed in the trenches respectively.

公开(公告)号：US20190204748A1

公开(公告)日：2019-07-04

申请号：US15872912

申请日：2018-01-16

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Feng-Ming Huang ,  Chien-Cheng Tsai

IPC分类号： G03F7/42 ,  H01L21/311

CPC分类号： G03F7/427 ,  H01L21/31138

摘要： A method for removing a patterned negative photoresist from a substrate includes: (a) placing the substrate on lift pins of a wafer chuck; (b) retracting the lift pins to place the substrate in a pin-down position and concurrently heating the substrate to a first temperature not exceeding 100° C.; (c) raising the lift pins to place the substrate in a pin-up position; (d) generating a plasma from a gas comprising NH3; and (e) exposing the substrate to the plasma in the pin-up position and the pin-down position alternatively to selectively remove the negative photoresist from the substrate.

公开(公告)号：US20180190664A1

公开(公告)日：2018-07-05

申请号：US15856022

申请日：2017-12-27

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Chien-Cheng Tsai ,  Feng-Ming Huang ,  Ying-Chiao Wang ,  Chien-Ting Ho ,  Li-Wei Feng ,  Tsung-Ying Tsai

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308

CPC分类号： H01L27/10894 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/3065 ,  H01L21/3081 ,  H01L27/10823 ,  H01L27/10876

摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first buried gate and a second buried gate in the substrate on the memory region; forming a first silicon layer on the substrate on the periphery region; forming a stacked layer on the first silicon layer; forming an epitaxial layer on the substrate between the first buried gate and the second buried gate; and forming a second silicon layer on the epitaxial layer on the memory region and the stacked layer on the periphery region.

公开(公告)号：US20230369215A1

公开(公告)日：2023-11-16

申请号：US18226750

申请日：2023-07-26

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chien-Cheng Tsai ,  Feng-Ming Huang

IPC分类号： H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/762 ,  H01L29/06 ,  H10B12/00

CPC分类号： H01L23/5283 ,  H01L21/31111 ,  H01L21/76831 ,  H01L23/5226 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76224 ,  H01L29/0649 ,  H10B12/482 ,  H10B12/485

摘要： A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

公开(公告)号：US11769727B2

公开(公告)日：2023-09-26

申请号：US17467287

申请日：2021-09-06

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chien-Cheng Tsai ,  Feng-Ming Huang

IPC分类号： H01L23/52 ,  H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/762 ,  H01L29/06 ,  H10B12/00

CPC分类号： H01L23/5283 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/0649 ,  H10B12/482 ,  H10B12/485

摘要： A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

公开(公告)号：US20210398902A1

公开(公告)日：2021-12-23

申请号：US17467287

申请日：2021-09-06

申请人： United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chien-Cheng Tsai ,  Feng-Ming Huang

IPC分类号： H01L23/528 ,  H01L21/311 ,  H01L27/108 ,  H01L21/768 ,  H01L23/522 ,  H01L21/762 ,  H01L29/06

摘要： A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

公开(公告)号：US10658365B2

公开(公告)日：2020-05-19

申请号：US16052636

申请日：2018-08-02

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Cheng Tsai ,  Chih-Chi Cheng ,  Chia-Wei Wu ,  Ger-Pin Lin

IPC分类号： H01L27/108

摘要： A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.

公开(公告)号：US10529719B2

公开(公告)日：2020-01-07

申请号：US15961827

申请日：2018-04-24

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Po-Han Wu ,  Li-Wei Feng ,  Shih-Han Hung ,  Fu-Che Lee ,  Chien-Cheng Tsai

IPC分类号： H01L27/108 ,  H01L21/768

摘要： A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.

公开(公告)号：US10151048B1

公开(公告)日：2018-12-11

申请号：US15825127

申请日：2017-11-29

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Wan-Chi Wu ,  Hui-Ling Chuang ,  Chih-Chi Cheng ,  Chiu-Hsien Yeh ,  Chien-Cheng Tsai ,  Hung-Jung Yan

IPC分类号： H01L21/00 ,  C30B25/18 ,  H01L27/108 ,  G11C11/4094 ,  H01L21/02 ,  G11C11/4097

摘要： A manufacturing method of an epitaxial contact structure in a semiconductor memory device includes the following steps. A recess is formed in a semiconductor substrate by an etching process. An etching defect is formed in the recess by the etching process. An oxidation process is performed after the etching process. An oxide layer is formed in the recess by the oxidation process, and the etching defect is encompassed by the oxide layer. A cleaning process is performed after the oxidation process. The oxide layer and the etching defect encompassed by the oxide layer are removed by the cleaning process. An epitaxial growth process is performed to form an epitaxial contact structure in the recess after the cleaning process.

公开(公告)号：US20180108563A1

公开(公告)日：2018-04-19

申请号：US15384940

申请日：2016-12-20

申请人： United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Chieh-Te Chen ,  Hsien-Shih Chu ,  Ming-Feng Kuo ,  Fu-Che Lee ,  Chien-Ting Ho ,  Chiung-Lin Hsu ,  Feng-Yi Chang ,  Yi-Wang Zhan ,  Li-Chiang Chen ,  Chien-Cheng Tsai ,  Chin-Hsin Chiu

IPC分类号： H01L21/762 ,  H01L21/308

CPC分类号： H01L21/76224 ,  H01L21/3081 ,  H01L21/762

摘要： A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.