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    Memory structure and manufacturing method thereof
    15.
    发明授权
    Memory structure and manufacturing method thereof 有权

    公开(公告)号：US11581325B2

    公开(公告)日：2023-02-14

    申请号：US17201986

    申请日：2021-03-15

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Hung Chen ,  Yu-Huang Yeh ,  Chuan-Fu Wang

    IPC: H01L27/11568 ,  H01L27/11565 ,  H01L27/11521 ,  H01L27/11519

    Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.

    RESISTIVE RANDOM-ACCESS MEMORY (RRAM) DEVICE AND FORMING METHOD THEREOF
    16.
    发明申请
    RESISTIVE RANDOM-ACCESS MEMORY (RRAM) DEVICE AND FORMING METHOD THEREOF 有权

    公开(公告)号：US20220399495A1

    公开(公告)日：2022-12-15

    申请号：US17378795

    申请日：2021-07-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L45/00

    Abstract: A RRAM device includes a bottom electrode, a resistive material layer, a high work function layer, a top electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the high work function layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming said RRAM device is also provided.

    RRAM STRUCTURE AND METHOD OF FABRICATING THE SAME
    18.
    发明申请
    RRAM STRUCTURE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210217813A1

    公开(公告)日：2021-07-15

    申请号：US16794194

    申请日：2020-02-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.

    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF
    19.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF 审中-公开

    公开(公告)号：US20200185399A1

    公开(公告)日：2020-06-11

    申请号：US16792847

    申请日：2020-02-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L27/11568 ,  H01L21/28 ,  H01L29/792

    Abstract: A method for fabricating a semiconductor memory device is disclosed. A substrate having a main surface is provided. A memory gate is formed on the main surface of the substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is formed in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is formed between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is formed on the first sidewall of the memory gate and a second single spacer structure on the fourth sidewall of the control gate. A gap-filling layer is formed to fill up the gap.

    MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF
    20.
    发明申请
    MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200083344A1

    公开(公告)日：2020-03-12

    申请号：US16123868

    申请日：2018-09-06

    Applicant: United Microelectronics Corp.

    Inventor： Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Chuan-Fu Wang ,  Yu-Huang Yeh

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/49 ,  H01L29/45

    Abstract: A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided. The first gate structure includes a first gate and a charge storage layer. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate.

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