公开(公告)号：US20220365433A1

公开(公告)日：2022-11-17

申请号：US17316736

申请日：2021-05-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Da-Jun Lin ,  Yao-Hsien Chung ,  Ting-An Chien ,  Bin-Siang Tsai ,  Chih-Wei Chang ,  Shih-Wei Su ,  Hsu Ting ,  Sung-Yuan Tsai

IPC: G03F7/075 ,  G03F7/20

Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.

公开(公告)号：US20220262939A1

公开(公告)日：2022-08-18

申请号：US17179322

申请日：2021-02-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Chang ,  Yao-Hsien Chung ,  Shih-Wei Su ,  Hao-Hsuan Chang ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is then subjected to an oxidation treatment or a nitridation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.

公开(公告)号：US11114331B2

公开(公告)日：2021-09-07

申请号：US16431684

申请日：2019-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Hung-Chun Lee ,  Shu-Ming Yeh ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311

Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a pad layer adjacent to two sides of trench; forming a dielectric layer to fill the trench; and performing a dry etching process to remove the pad layer and part of the dielectric layer to form a shallow trench isolation (STI). Preferably, the dry etching process comprises a non-plasma etching process.

公开(公告)号：US10892348B2

公开(公告)日：2021-01-12

申请号：US16396788

申请日：2019-04-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Bin-Siang Tsai ,  Ting-An Chien ,  Yi-Liang Ye

IPC: H01L29/66 ,  H01L21/62 ,  H01L21/02 ,  H01L21/265 ,  H01L21/308 ,  H01L21/762 ,  H01L29/78

Abstract: A method of rounding fin-shaped structures includes the following steps. A substrate including fin-shaped structures, and pad oxide caps and pad nitride caps covering the fin-shaped structures from bottom to top are provided. An isolation structure fills between the fin-shaped structures. A removing process is performed to remove a top part of the isolation structure and expose top parts of the fin-shaped structures. An oxidation process is performed to oxidize sidewalls of the top parts of the fin-shaped structures, thereby forming oxidized parts covering sidewalls of the top parts of the fin-shaped structures. The pad nitride caps are removed. The pad oxide caps and the oxidized parts are removed at the same time, thereby forming rounding fin-shaped structures.

公开(公告)号：US20200343371A1

公开(公告)日：2020-10-29

申请号：US16396788

申请日：2019-04-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Bin-Siang Tsai ,  Ting-An Chien ,  Yi-Liang Ye

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/308

Abstract: A method of rounding fin-shaped structures includes the following steps. A substrate including fin-shaped structures, and pad oxide caps and pad nitride caps covering the fin-shaped structures from bottom to top are provided. An isolation structure fills between the fin-shaped structures. A removing process is performed to remove a top part of the isolation structure and expose top parts of the fin-shaped structures. An oxidation process is performed to oxidize sidewalls of the top parts of the fin-shaped structures, thereby forming oxidized parts covering sidewalls of the top parts of the fin-shaped structures. The pad nitride caps are removed. The pad oxide caps and the oxidized parts are removed at the same time, thereby forming rounding fin-shaped structures.

公开(公告)号：US20200052123A1

公开(公告)日：2020-02-13

申请号：US16056540

申请日：2018-08-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Chun-Wei Yu ,  Yu-Ren Wang ,  Hao-Hsuan Chang ,  Chia-Wei Hsu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762

Abstract: A method of rounding corners of a fin includes providing a substrate with a fin protruding from the substrate, wherein a pad oxide and a pad nitride entirely cover a top surface of the fin. Later, part of the pad oxide is removed laterally to expose part of the top surface of the fin. A silicon oxide layer is formed to contact two sidewalls of the fin and the exposed top surface, wherein two sidewalls and the top surface define two corners of the fin. After forming the silicon oxide layer, an annealing process is performed to round two corners of the fin. Finally, after the annealing process, an STI filling material is formed to cover the pad nitride, the pad oxide and the fin.

公开(公告)号：US12015076B2

公开(公告)日：2024-06-18

申请号：US18092916

申请日：2023-01-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Chang ,  Yao-Hsien Chung ,  Shih-Wei Su ,  Hao-Hsuan Chang ,  Da-Jun Lin ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/7786

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed on the gate.

公开(公告)号：US11762293B2

公开(公告)日：2023-09-19

申请号：US17316736

申请日：2021-05-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Da-Jun Lin ,  Yao-Hsien Chung ,  Ting-An Chien ,  Bin-Siang Tsai ,  Chih-Wei Chang ,  Shih-Wei Su ,  Hsu Ting ,  Sung-Yuan Tsai

IPC: G03F7/075 ,  G03F7/20 ,  C23C16/34

CPC classification number: G03F7/0755 ,  G03F7/2043 ,  C23C16/345

Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.

公开(公告)号：US20230163207A1

公开(公告)日：2023-05-25

申请号：US17834936

申请日：2022-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Chang ,  Da-Jun Lin ,  Yao-Hsien Chung ,  Shih-Wei Su ,  Hao-Hsuan Chang ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66462

Abstract: The invention provides a semiconductor structure, which comprises a GaN gallium nitride (GaN) layer, an aluminum gallium nitride (AlGaN) layer on the gallium nitride layer, a polarization boost layer on and in direct contact with the aluminum gallium nitride layer, and a gate liner layer on the polarization boost layer.

公开(公告)号：US20220165866A1

公开(公告)日：2022-05-26

申请号：US17143135

申请日：2021-01-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Chang ,  Yao-Hsien Chung ,  Shih-Wei Su ,  Hao-Hsuan Chang ,  Da-Jun Lin ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed directly on the gate.