公开(公告)号：US20220181505A1

公开(公告)日：2022-06-09

申请号：US17145416

申请日：2021-01-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Li Lin ,  Wei-Da Lin ,  Cheng-Guo Chen ,  Ta-Kang Lo ,  Yi-Chuan Chen ,  Huan-Chi Ma ,  Chien-Wen Yu ,  Kuan-Ting Lu ,  Kuo-Yu Liao

IPC: H01L29/94 ,  H01L29/66

Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

公开(公告)号：US10707305B2

公开(公告)日：2020-07-07

申请号：US16354126

申请日：2019-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Guo Chen ,  Kun-Yuan Wu ,  Tai-You Chen ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/739 ,  H01L29/267

Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

公开(公告)号：US20190214463A1

公开(公告)日：2019-07-11

申请号：US16354126

申请日：2019-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Guo Chen ,  Kun-Yuan Wu ,  Tai-You Chen ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo

IPC: H01L29/08 ,  H01L29/739 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66636 ,  H01L29/7391 ,  H01L29/7848 ,  H01L29/785

Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

公开(公告)号：US20190115259A1

公开(公告)日：2019-04-18

申请号：US15803865

申请日：2017-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jiun-Lin Yeh ,  Hsueh-Chih Tseng ,  Chia-Chen Tsai ,  Ta-Kang Lo

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/266

Abstract: A manufacturing method of a semiconductor device includes following steps. First gate structures and second gate structures are formed on a first region and a second region of a semiconductor substrate respectively. A spacing distance between the second gate structures is larger than that between the first gate structures. A first ion implantation is preformed to form a first doped region between the first gate structures. A second ion implantation is performed to form a second doped region between the second gate structures. A tilt angle of the second ion implantation is larger than that of the first ion implantation. An implantation dose of the second ion implantation is lower than that of the first ion implantation. An etching process is performed to at least partially remove the first doped region to form a first recess and at least partially remove the second doped region to form a second recess.

公开(公告)号：US12278282B2

公开(公告)日：2025-04-15

申请号：US17742383

申请日：2022-05-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Li Lin ,  Cheng-Guo Chen ,  Ta-Kang Lo ,  Cheng-Han Wu

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66

Abstract: A high-electron mobility transistor includes a substrate, a gate electrode, a drain electrode, a source electrode and a first field plate. The substrate includes an active region. The gate electrode is disposed on the substrate. The drain electrode is disposed at one side of the gate electrode. The source electrode is disposed at another side of the gate electrode. The first field plate is electrically connected with the source electrode and extends from the source electrode toward the drain electrode. An overlapping area of the first field plate and the gate electrode is smaller than an overlapping area of the gate electrode and the active region.

公开(公告)号：US10607891B2

公开(公告)日：2020-03-31

申请号：US15803865

申请日：2017-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jiun-Lin Yeh ,  Hsueh-Chih Tseng ,  Chia-Chen Tsai ,  Ta-Kang Lo

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/265 ,  H01L21/266 ,  H01L27/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/84

Abstract: A manufacturing method of a semiconductor device includes following steps. First gate structures and second gate structures are formed on a first region and a second region of a semiconductor substrate respectively. A spacing distance between the second gate structures is larger than that between the first gate structures. A first ion implantation is preformed to form a first doped region between the first gate structures. A second ion implantation is performed to form a second doped region between the second gate structures. A tilt angle of the second ion implantation is larger than that of the first ion implantation. An implantation dose of the second ion implantation is lower than that of the first ion implantation. An etching process is performed to at least partially remove the first doped region to form a first recess and at least partially remove the second doped region to form a second recess.

公开(公告)号：US10276663B2

公开(公告)日：2019-04-30

申请号：US15213370

申请日：2016-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Guo Chen ,  Kun-Yuan Wu ,  Tai-You Chen ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/739 ,  H01L29/267

Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

公开(公告)号：US20180019341A1

公开(公告)日：2018-01-18

申请号：US15213370

申请日：2016-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Guo Chen ,  Kun-Yuan Wu ,  Tai-You Chen ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66636 ,  H01L29/7391 ,  H01L29/7848 ,  H01L29/785

Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

公开(公告)号：US09685520B1

公开(公告)日：2017-06-20

申请号：US15355032

申请日：2016-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shuo-Lin Hsu ,  Hsin-Ta Hsieh ,  Chun-Chia Chen ,  Chen-Chien Li ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L21/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66666

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first gate dielectric layer is formed in a first gate trench and a second gate dielectric layer is formed in a second gate trench. A first bottom barrier layer is formed on the first gate dielectric layer and the second gate dielectric layer. A first conductivity type work function layer is formed on the first bottom barrier layer. A first treatment to the first gate dielectric layer and/or a second treatment to the first bottom barrier layer on the first gate dielectric layer are performed before the step of forming the first conductivity type work function layer. The first treatment and the second treatment are used to modify threshold voltages of specific transistors, and thicknesses of work function layers formed subsequently may be modified for increasing the related process window accordingly.