公开(公告)号：US20210210628A1

公开(公告)日：2021-07-08

申请号：US17207751

申请日：2021-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Shou-Wei Hsieh ,  Chih-Ming Su ,  Yi-Ren Chen ,  Yuan-Ting Chuang

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/417

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

公开(公告)号：US12249649B2

公开(公告)日：2025-03-11

申请号：US17207751

申请日：2021-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Shou-Wei Hsieh ,  Chih-Ming Su ,  Yi-Ren Chen ,  Yuan-Ting Chuang

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/417

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

公开(公告)号：US20230335630A1

公开(公告)日：2023-10-19

申请号：US17742383

申请日：2022-05-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Li Lin ,  Cheng-Guo Chen ,  Ta-Kang Lo ,  Cheng-Han Wu

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7786 ,  H01L29/66462 ,  H01L29/404

Abstract: A high-electron mobility transistor includes a substrate, a gate electrode, a drain electrode, a source electrode and a first field plate. The substrate includes an active region. The gate electrode is disposed on the substrate. The drain electrode is disposed at one side of the gate electrode. The source electrode is disposed at another side of the gate electrode. The first field plate is electrically connected with the source electrode and extends from the source electrode toward the drain electrode. An overlapping area of the first field plate and the gate electrode is smaller than an overlapping area of the gate electrode and the active region.

公开(公告)号：US10991824B2

公开(公告)日：2021-04-27

申请号：US16252715

申请日：2019-01-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Shou-Wei Hsieh ,  Chih-Ming Su ,  Yi-Ren Chen ,  Yuan-Ting Chuang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/417

Abstract: A semiconductor device includes: a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure; a second gate structure on the STI; and a third gate structure on the SDB structure, wherein a width of the third gate structure is greater than a width of the second gate structure.

公开(公告)号：US09147601B2

公开(公告)日：2015-09-29

申请号：US14541148

申请日：2014-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Chun-Chi Yu

IPC: H01L21/311 ,  H01L21/302 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/027

CPC classification number: H01L21/76816 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139

Abstract: The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned layer is formed on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer. The patterned layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.

Abstract translation: 本发明提供一种形成通孔的方法。 首先，提供基板。 在基板上限定多个第一区域。 在基板上形成介电层和阻挡层。 在阻挡层上形成图案层，使得阻挡层的侧壁被图案化层完全覆盖。 图案化层包括以规则阵列布置的多个孔，其中孔阵列的面积大于第一区域的面积。 通过使用图案化层作为掩模来去除第一区域中的阻挡层。 最后，电介质层被图案化以在第一区域中的电介质层中至少形成通孔。

公开(公告)号：US20150072529A1

公开(公告)日：2015-03-12

申请号：US14541148

申请日：2014-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Chun-Chi Yu

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/76816 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139

Abstract: The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned layer is formed on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer. The patterned layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.

Abstract translation: 本发明提供一种形成通孔的方法。 首先，提供基板。 在基板上限定多个第一区域。 在基板上形成介电层和阻挡层。 在阻挡层上形成图案层，使得阻挡层的侧壁被图案化层完全覆盖。 图案化层包括以规则阵列布置的多个孔，其中孔阵列的面积大于第一区域的面积。 通过使用图案化层作为掩模来去除第一区域中的阻挡层。 最后，电介质层被图案化以在第一区域中的电介质层中至少形成通孔。