公开(公告)号：US20170178716A1

公开(公告)日：2017-06-22

申请号：US15448599

申请日：2017-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Yu-Cheng Tung ,  Chin-Sheng Yang

IPC: G11C11/417 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

公开(公告)号：US09613969B2

公开(公告)日：2017-04-04

申请号：US14793714

申请日：2015-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Wei-Cyuan Lo ,  Ming-Jui Chen ,  Chia-Lin Lu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Shu-Ru Wang ,  Yung-Feng Cheng

IPC: H01L27/11 ,  H01L29/76 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L21/823871 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/7851 ,  H01L29/7853

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

公开(公告)号：US20160351575A1

公开(公告)日：2016-12-01

申请号：US14793714

申请日：2015-07-07

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Wei-Cyuan Lo ,  Ming-Jui Chen ,  Chia-Lin Lu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Shu-Ru Wang ,  Yung-Feng Cheng

IPC: H01L27/11 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L21/823871 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/7851 ,  H01L29/7853

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

Abstract translation: 本发明提供一种半导体结构，其包括基板，多个翅片结构，多个栅极结构，电介质层和多个接触插塞。 衬底具有存储区域。 翅片结构设置在存储区域中的基板上，每个沿着第一方向延伸。 栅极结构设置在翅片结构上，每个翼结构沿着第二方向延伸。 电介质层设置在栅极结构和鳍结构上。 接触插头设置在电介质层中并电连接到鳍结构中的源极/漏极区域。 从顶部看，接触塞具有梯形或五边形。 本发明还提供了一种形成该方法的方法。