公开(公告)号：US11895927B2

公开(公告)日：2024-02-06

申请号：US17319106

申请日：2021-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chang Hsu ,  Tang-Chun Weng ,  Cheng-Yi Lin ,  Yung-Shen Chen ,  Chia-Hung Lin

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

公开(公告)号：US20220344579A1

公开(公告)日：2022-10-27

申请号：US17319106

申请日：2021-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chang Hsu ,  Tang-Chun Weng ,  Cheng-Yi Lin ,  Yung-Shen Chen ,  Chia-Hung Lin

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

公开(公告)号：US10170623B2

公开(公告)日：2019-01-01

申请号：US15796874

申请日：2017-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Tang-Chun Weng ,  Chien-Hao Chen

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. The trench is disposed between the fin shaped structures. The spacing layer is disposed on sidewalls of the trench, wherein the spacing layer has a top surface lower than a top surface of the fin shaped structures. The dummy gate structure is disposed on the fin shaped structures and across the trench.