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11.发明授权Method of fabricating high voltage metal-oxide-semiconductor transistor device 有权制造高压金属氧化物半导体晶体管器件的方法公开(公告)号：US09034713B2
公开(公告)日：2015-05-19
申请号：US14548248
申请日：2014-11-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Chung Wang , Wei-Lun Hsu , Shan-Shi Huang , Ke-Feng Lin , Te-Yuan Wu
IPC: H01L29/78 , H01L21/336 , H01L29/66 , H01L29/40 , H01L29/06 , H01L29/08 , H01L21/266 , H01L21/033
CPC classification number: H01L29/66681 , H01L21/0334 , H01L21/266 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/42368 , H01L29/4238 , H01L29/66659 , H01L29/7816
Abstract: The present invention provides a method of fabricating a HV MOS transistor device, including forming a deep well in a substrate, and the deep well; forming a first doped region in the deep well, and the first doped region, wherein a doping concentration of the first doped region and a doping concentration of the deep well in at least one electric field concentration region has a first ratio, the doping concentration of the first doped region and the doping concentration of the deep well outside the electric field concentration region has a second ratio, and the first ratio is greater than the second ratio; and forming a high voltage well in the substrate, and forming a second doped region and a third doped region respectively in the deep well and in the high voltage well.
Abstract translation: 本发明提供一种制造HV MOS晶体管器件的方法，包括在衬底和深阱中形成深阱; 在所述深阱中形成第一掺杂区域和所述第一掺杂区域，其中所述第一掺杂区域的掺杂浓度和所述深阱在至少一个电场浓度区域中的掺杂浓度具有第一比率，所述第一掺杂区域的掺杂浓度 第一掺杂区域和电场浓度区外的深阱的掺杂浓度具有第二比例，第一比值大于第二比例; 以及在所述衬底中形成高电压阱，以及分别在所述深阱和所述高电压阱中形成第二掺杂区和第三掺杂区。
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12.发明授权公开(公告)号：US11916075B2
公开(公告)日：2024-02-27
申请号：US17741123
申请日：2022-05-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei-Lun Hsu , Yung-Chien Kung , Ming-Tsung Yeh , Yan-Hsiu Liu , Am-Tay Luy , Yao-Pi Hsu , Ji-Fu Kung
IPC: H01L29/423 , H01L27/092 , H01L21/762 , H01L21/8238 , H01L21/761 , H01L21/8234 , H01L29/78
CPC classification number: H01L27/0922 , H01L21/761 , H01L21/76224 , H01L21/823878 , H01L21/823481 , H01L21/823892 , H01L29/7813
Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
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公开(公告)号：US10795255B2
公开(公告)日：2020-10-06
申请号：US16175858
申请日：2018-10-31
Inventor： Wei-Lun Hsu , Gang-Yi Lin , Yu-Hsiang Hung , Ying-Chih Lin , Feng-Yi Chang , Ming-Te Wei , Shih-Fang Tzou , Fu-Che Lee , Chia-Liang Liao
IPC: G03F1/36 , H01L23/538 , G03F1/38 , H01L21/033 , H01L21/308 , G03F1/00 , G03F7/20 , G03F7/00 , H01L27/108
Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.
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公开(公告)号：US10770464B2
公开(公告)日：2020-09-08
申请号：US15896091
申请日：2018-02-14
Inventor： Chih-Chien Liu , Chia-Lung Chang , Tzu-Chin Wu , Wei-Lun Hsu
IPC: H01L23/532 , H01L27/108
Abstract: A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.
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15.发明授权公开(公告)号：US10529715B2
公开(公告)日：2020-01-07
申请号：US15427512
申请日：2017-02-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei-Lun Hsu , Yung-Chien Kung , Ming-Tsung Yeh , Yan-Hsiu Liu , Am-Tay Luy , Yao-Pi Hsu , Ji-Fu Kung
IPC: H01L21/304 , H01L27/092 , H01L21/762 , H01L21/8238 , H01L21/761 , H01L21/8234 , H01L29/78
Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
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Patent Agency Ranking
公开(公告)号：US20190221570A1
公开(公告)日：2019-07-18
申请号：US15896091
申请日：2018-02-14
Inventor： Chih-Chien Liu , Chia-Lung Chang , Tzu-Chin Wu , Wei-Lun Hsu
IPC: H01L27/108 , H01L23/532
Abstract: A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.
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公开(公告)号：US10910386B2
公开(公告)日：2021-02-02
申请号：US15943721
申请日：2018-04-03
Inventor： Wei-Lun Hsu , Hung-Lin Shih , Che-Hung Huang , Ping-Cheng Hsu , Hsu-Yang Wang
IPC: H01L27/10 , H01L27/108 , H01L21/768 , H01L21/762 , H01L21/8234 , H01L21/8238
Abstract: According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; and forming a bit line structure in the trench.
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公开(公告)号：US20200105764A1
公开(公告)日：2020-04-02
申请号：US16175858
申请日：2018-10-31
Inventor： Wei-Lun Hsu , Gang-Yi Lin , Yu-Hsiang Hung , Ying-Chih Lin , Feng-Yi Chang , Ming-Te Wei , Shih-Fang Tzou , Fu-Che Lee , Chia-Liang Liao
IPC: H01L27/108 , G11C11/402 , H01L23/538
Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.
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公开(公告)号：US20200035782A1
公开(公告)日：2020-01-30
申请号：US16116859
申请日：2018-08-29
Inventor： Li-Wei Feng , En-Chiuan Liou , Yu-Cheng Tung , Wei-Lun Hsu , Yu-Hsiang Hung , Ming-Te Wei , Le-Tien Jung
Abstract: The present invention provides a semiconductor structure including a substrate including a plurality of capacitor lower electrodes, the capacitor lower electrodes are arranged in a diamond array along a first direction and a second direction respectively, the first direction and the second direction are not perpendicular to each other. A supporting structure layer contacts at least parts of the capacitor lower electrodes, wherein the supporting structure layer includes a plurality of triangular openings, and the three corners of each triangular opening are overlapped with three adjacent capacitor lower electrodes respectively.
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20.发明申请公开(公告)号：US20180204838A1
公开(公告)日：2018-07-19
申请号：US15427512
申请日：2017-02-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei-Lun Hsu , Yung-Chien Kung , Ming-Tsung Yeh , Yan-Hsiu Liu , Am-Tay Luy , Yao-Pi Hsu , Ji-Fu Kung
IPC: H01L27/092 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/304
Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
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