公开(公告)号：US20220139762A1

公开(公告)日：2022-05-05

申请号：US17133652

申请日：2020-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  JI FENG ,  GUOHAI ZHANG ,  CHING HWA TEY

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/02

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US20210134653A1

公开(公告)日：2021-05-06

申请号：US16673929

申请日：2019-11-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： JI FENG ,  Yunfei Li ,  GUOHAI ZHANG ,  CHING HWA TEY ,  JINGLING WANG

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/265

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate is provided and the substrate has a first semiconductor layer formed thereon. Next, an isolating structure is formed in the first semiconductor layer, and a sacrificial layer is formed on the first semiconductor layer by consuming a top portion of the first semiconductor layer. Then, the sacrificial layer is removed to form a second semiconductor layer, and a portion of the isolating structure is also removed to form a shallow trench isolation (STI), with a top surface of the shallow trench isolation being substantially coplanar with a top surface of the second semiconductor layer.

公开(公告)号：US20170117150A1

公开(公告)日：2017-04-27

申请号：US15401086

申请日：2017-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Duan Quan Liao ,  Yikun Chen ,  CHING HWA TEY

IPC: H01L21/033 ,  H01L21/308

CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/0657 ,  H01L29/66553

Abstract: A semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.

公开(公告)号：US20150140800A1

公开(公告)日：2015-05-21

申请号：US14082200

申请日：2013-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Cheng ,  Ming Sheng Xu ,  Duan Quan Liao ,  Yikun Chen ,  CHING HWA TEY

IPC: H01L21/28 ,  H01L21/8234

CPC classification number: H01L21/28132 ,  H01L21/28273 ,  H01L21/823468 ,  H01L27/11524

Abstract: A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.

Abstract translation: 制造半导体器件的方法包括以下步骤。 提供至少一个第一栅堆叠层和至少一个从衬底上的导电层突出的第二栅堆叠层。 随后，在导电层上形成两个间隔物和保护层，两个间隔物和保护层共同围绕突出的第一栅叠层和突出的第二栅堆叠层。 将两个间隔物和保护层用作掩模以去除导电层的一部分。 之后，取下两个间隔物和保护层。