公开(公告)号：US11476192B2

公开(公告)日：2022-10-18

申请号：US16734373

申请日：2020-01-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L23/528 ,  H01L29/08 ,  H01L29/78 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H03F3/16 ,  H01L21/321 ,  H01L21/84

Abstract: A semiconductor device includes: a first gate line and a second gate line extending only along a first direction, a third gate line and a fourth gate line extending along the first direction and between the first gate line and the second gate line, a fifth gate line and a sixth gate line extending along a second direction between the first gate line and the second gate line and intersecting the third gate line and the fourth gate line, and first contact plugs on the first gate line. Preferably, the first direction is perpendicular to the second direction and the first gate line and the second gate line are directly connected to the fifth gate line and the sixth gate line.

公开(公告)号：US11462489B2

公开(公告)日：2022-10-04

申请号：US17401335

申请日：2021-08-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/00 ,  H01L27/12 ,  H01L21/84 ,  H01L23/58 ,  H01L23/66 ,  H01L27/06

Abstract: A method of forming integrated circuit device, including: providing a substrate; forming an integrated circuit region on the substrate, the integrated circuit region comprising a dielectric stack; forming a seal ring in the dielectric stack and around a periphery of the integrated circuit region; forming a trench around the seal ring and the trench exposing a sidewall of the dielectric stack; forming a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack; and forming a passivation layer over the moisture blocking layer.

公开(公告)号：US20220270973A1

公开(公告)日：2022-08-25

申请号：US17204966

申请日：2021-03-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Su Xing ,  Shyam Parthasarathy

IPC: H01L23/538 ,  H01L25/065 ,  H01L27/06 ,  H01L23/552 ,  H01L21/50 ,  H01L21/768

Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device wafer includes a first insulating layer, a first device layer on the first insulating layer, and a first bonding layer on the first device layer. The second device wafer includes a second insulating layer, a second device layer on a first side of the second insulating layer, and a second bonding layer on the second device layer. The second device layer includes a second device region and a second transistor in the second device region. The second device wafer is bonded to the first device wafer by bonding the second bonding layer with the first bonding layer. A shielding structure is on a second side of the second insulating layer opposite to the first side and vertically overlapped with the second device region.

公开(公告)号：US20220230975A1

公开(公告)日：2022-07-21

申请号：US17715067

申请日：2022-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Wen-Shen Li ,  Ching-Yang Wen

IPC: H01L23/66 ,  H01L21/762 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48 ,  H01L21/768 ,  H01L23/528

Abstract: A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.

公开(公告)号：US20210359131A1

公开(公告)日：2021-11-18

申请号：US17391048

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A LDMOS device includes a semiconductor layer on an insulation layer and a ring shape gate on the semiconductor layer. The ring shape gate includes a first gate portion, a second gate portion, and two third gate portions connecting the first gate portion and the second gate portion. The semiconductor device further includes a first drain region and a second drain region formed in the semiconductor layer at two sides of the ring shape gate, a plurality of source regions formed in the semiconductor layer surrounded by the ring shape gate, a plurality of body contact regions formed in the semiconductor layer and arranged between the source regions, and a first body implant region and a second body implant region formed in the semiconductor layer, respectively underlying part of the first gate portion and part of the second gate portion, and being connected by the body contact regions.

公开(公告)号：US20210104602A1

公开(公告)日：2021-04-08

申请号：US17124124

申请日：2020-12-16

Applicant: United Microelectronics Corp.

Inventor： Wen-Shen Li ,  Ching-Yang Wen ,  Purakh Raj Verma ,  Xingxing Chen ,  Chee-Hau Ng

IPC: H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/306 ,  H01L21/311

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.

公开(公告)号：US20200211899A1

公开(公告)日：2020-07-02

申请号：US16811830

申请日：2020-03-06

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang

IPC: H01L21/8249 ,  H01L21/768 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/66

Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device, a bipolar junction transistor (BJT), and a first interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The first interconnect structure is electrically connected to the base at the first side of the substrate and extends to the second side of the substrate.

公开(公告)号：US10529854B1

公开(公告)日：2020-01-07

申请号：US16109714

申请日：2018-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chih-Wei Su ,  Je-Min Wen

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/764 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; forming a metal-oxide semiconductor (MOS) transistor on the substrate; forming an interlayer dielectric layer (ILD) on the MOS transistor; removing part of the ILD layer to form a first trench to expose the insulating layer; and performing a wet etching process through the first trench to remove part of the insulating layer for forming a first air gap under the MOS transistor.

公开(公告)号：US20200006519A1

公开(公告)日：2020-01-02

申请号：US16054963

申请日：2018-08-03

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/12 ,  H01L21/768

Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device and a bipolar junction transistor (BJT) is provided. The CMOS device includes an N-type metal oxide semiconductor (NMOS) transistor and a P-type metal oxide semiconductor (PMOS) transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The semiconductor structure can have better overall performance.

公开(公告)号：US10411110B1

公开(公告)日：2019-09-10

申请号：US16053657

申请日：2018-08-02

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: A semiconductor structure including a substrate, a BJT, a first interconnect structure and a second interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The BJT is located at the first side. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. The first interconnect structure is located at the first side and electrically connected to the base. The second interconnect structure is located at the second side and electrically connected to the collector. The first interconnect structure further extends to the second side. The first interconnect structure and the second interconnect structure are respectively electrically connected to an external circuit at the second side. The semiconductor structure can have better overall performance.