公开(公告)号：US12119342B2

公开(公告)日：2024-10-15

申请号：US18119253

申请日：2023-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Te-Wei Yeh ,  Yi-Chun Chen

IPC: H01L27/06 ,  H01L21/306 ,  H01L21/765 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L49/02

CPC classification number: H01L27/0605 ,  H01L21/30621 ,  H01L21/765 ,  H01L21/8252 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786

Abstract: A resistor with GaN structures, including a GaN layer with a 2DEG resistor region and an undoped polysilicon resistor region, an AlGaN barrier layer on the GaN layer in the 2DEG resistor region, multiple p-type doped GaN capping layers arranged on the AlGaN barrier layer so that the GaN layer not covered by the p-type doped GaN capping layers in the 2DEG resistor region is converted into a 2DEG resistor, a passivation layer on the GaN layer, and an undoped polysilicon layer on the passivation layer in the undoped polysilicon resistor region and functions as an undoped polysilicon resistor.

公开(公告)号：US09691754B2

公开(公告)日：2017-06-27

申请号：US14691126

申请日：2015-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mei-Ling Chao ,  Yi-Chun Chen ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/36

CPC classification number: H01L27/0266 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/36

Abstract: A semiconductor structure comprises a well, a first lightly doped region, a second lightly doped region, a first heavily doped region, a second heavily doped region and a gate. The first lightly doped region is disposed in the well. The second lightly doped region is disposed in the well and separated from the first lightly doped region. The first heavily doped region is disposed in the first lightly doped region. The second heavily doped region is partially disposed in the second lightly doped region. The second heavily doped region has a surface contacting the well. The gate is disposed on the well between the first heavily doped region and the second heavily doped region. The well has a first doping type. The first lightly doped region, the second lightly doped region, the first heavily doped region and the second heavily doped region have a second doping type.

公开(公告)号：US09142545B2

公开(公告)日：2015-09-22

申请号：US14181740

申请日：2014-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Chun Chen ,  Li-Cih Wang ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L27/06

CPC classification number: H01L27/0262 ,  H01L27/0259 ,  H01L27/0921

Abstract: The electrostatic discharge protection structure includes an N-well disposed on a substrate, a P-well disposed on the substrate and adjacent to the N-well, a first doped region of N-type conductivity disposed in the N-well, a second doped region of N-type conductivity disposed in the N-well, a third doped region of P-type conductivity disposed in the N-well, a fifth doped region of P-type conductivity disposed in the P-well, a fourth doped region of N-type conductivity disposed between the third doped region and the fifth doped region in the P-well, an anode electrically connected to the first doped region and the second doped region, and a cathode electrically connected to the fourth doped region and the fifth doped region.

Abstract translation: 静电放电保护结构包括设置在衬底上的N阱，设置在衬底上并与N阱相邻的P阱，设置在N阱中的N型导电性的第一掺杂区，第二掺杂 设置在N阱中的N型导电性区域，设置在N阱中的P型导电体的第三掺杂区域，设置在P阱中的P型导电性的第五掺杂区域，第四掺杂区域 设置在P阱中的第三掺杂区域和第五掺杂区域之间的N型导电体，与第一掺杂区域和第二掺杂区域电连接的阳极，以及电连接到第四掺杂区域和第五掺杂区域的阴极 地区。

公开(公告)号：US20150236010A1

公开(公告)日：2015-08-20

申请号：US14181740

申请日：2014-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Chun Chen ,  Li-Cih Wang ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L27/06

CPC classification number: H01L27/0262 ,  H01L27/0259 ,  H01L27/0921

Abstract: The electrostatic discharge protection structure includes an N-well disposed on a substrate, a P-well disposed on the substrate and adjacent to the N-well, a first doped region of N-type conductivity disposed in the N-well, a second doped region of N-type conductivity disposed in the N-well, a third doped region of P-type conductivity disposed in the N-well, a fifth doped region of P-type conductivity disposed in the P-well, a fourth doped region of N-type conductivity disposed between the third doped region and the fifth doped region in the P-well, an anode electrically connected to the first doped region and the second doped region, and a cathode electrically connected to the fourth doped region and the fifth doped region.

Abstract translation: 静电放电保护结构包括设置在衬底上的N阱，设置在衬底上并与N阱相邻的P阱，设置在N阱中的N型导电性的第一掺杂区，第二掺杂 设置在N阱中的N型导电性区域，设置在N阱中的P型导电体的第三掺杂区域，设置在P阱中的P型导电性的第五掺杂区域，第四掺杂区域 设置在P阱中的第三掺杂区域和第五掺杂区域之间的N型导电体，与第一掺杂区域和第二掺杂区域电连接的阳极，以及电连接到第四掺杂区域和第五掺杂区域的阴极 地区。