公开(公告)号：US5849440A

公开(公告)日：1998-12-15

申请号：US792670

申请日：1997-01-29

Applicant: Kevin D. Lucas ,  Michael E. Kling ,  Alfred J. Reich ,  Chong-Cheng Fu ,  James Morrow

Inventor： Kevin D. Lucas ,  Michael E. Kling ,  Alfred J. Reich ,  Chong-Cheng Fu ,  James Morrow

IPC: G03F1/00 ,  G03F1/84 ,  G03F7/20 ,  H01L21/027 ,  G03F9/00

CPC classification number: G03F7/705 ,  G03F1/84 ,  G03F7/70433 ,  G03F7/70633

Abstract: A process for fabricating a semiconductor device includes the formation of a lithographic reticle (20) having a lithographic pattern (18) overlying a reticle substrate (10). In one embodiment, a reticle inspection database incorporates altered resolution assisting features (30,32) to inspect the lithographic pattern (18). The dimensional difference between the reticle inspection database and the lithographic reticle is substantially equal to the process bias realized during reticle fabrication. Inspection of the lithographic reticle (20) using a reticle inspection database containing altered resolution assisting features reduces the false detection of defects and provides increased sensitivity in the reticle inspection process.

Abstract translation: 一种用于制造半导体器件的工艺包括形成具有覆盖在掩模版衬底（10）上的平版印刷图案（18）的光刻掩模版（20）。 在一个实施例中，掩模版检查数据库包含改变的分辨率辅助特征（30,32）以检查光刻图案（18）。 标线检查数据库和光刻掩模版之间的尺寸差异基本上等于在掩模版制造期间实现的工艺偏差。 使用包含改变的分辨率辅助特征的掩模版检查数据库对光刻掩模版（20）的检查减少了缺陷的错误检测并且在掩模版检查过程中提供了增加的灵敏度。

公开(公告)号：US07235473B2

公开(公告)日：2007-06-26

申请号：US11213470

申请日：2005-08-26

Applicant: Dharmesh Jawarani ,  Chong-Cheng Fu ,  Mark D. Hall

Inventor： Dharmesh Jawarani ,  Chong-Cheng Fu ,  Mark D. Hall

IPC: H01L21/4763

CPC classification number: H01L29/66507

Abstract: A semiconductor fabrication process includes forming a gate stack overlying semiconductor substrate. Source/drain regions are formed in the substrate laterally aligned to the gate stack. A hard mask is formed overlying a gate electrode of the gate stack. A first silicide is then formed selectively over the source/drain regions. After removing the hard mask, a second silicide is selectively formed on the gate electrode. The first silicide and the second silicide are different. Forming the gate stack may include forming a gate dielectric on the semiconductor substrate and a polysilicon gate electrode on the gate dielectric. The gate electrode may have a line width of less than 40 nm. Forming the second silicide may include forming nickel silicide in upper portions of the gate electrode.

公开(公告)号：US07132327B2

公开(公告)日：2006-11-07

申请号：US10853701

申请日：2004-05-25

Applicant: Tab A. Stephens ,  Chong-Cheng Fu ,  Charles F. King

Inventor： Tab A. Stephens ,  Chong-Cheng Fu ,  Charles F. King

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/32139 ,  H01L21/28123

Abstract: A patterning method allows for separate transfer of a complementary reticle set. In one embodiment, for example, the method includes etching a phase shift mask (PSM), then etching a cut mask for a cPSM mask. Moreover, a decoupled complementary mask patterning transfer method includes two separate and decoupled mask patterning steps which form combined patterns through the use of partial image transfers into an intermediate hard mask prior to final wafer patterning. The intermediate and final hard mask materials are chosen to prevent image transfer into an underlying substrate or wafer prior to the final etch process.

Abstract translation: 图案化方法允许互补掩模版集合的单独转移。 在一个实施例中，例如，该方法包括蚀刻相移掩模（PSM），然后蚀刻用于cPSM掩模的切割掩模。 此外，解耦互补掩模图案转移方法包括两个单独的和去耦的掩模图案化步骤，其通过在最终的晶片图案化之前通过使用部分图像转移到中间硬掩模中形成组合图案。 选择中间和最终硬掩模材料以防止在最终蚀刻工艺之前图像转移到下面的基底或晶片中。

公开(公告)号：US20050277276A1

公开(公告)日：2005-12-15

申请号：US10853701

申请日：2004-05-25

Applicant: Tab Stephens ,  Chong-Cheng Fu ,  Charles King

Inventor： Tab Stephens ,  Chong-Cheng Fu ,  Charles King

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/4763 ,  H01L21/8222

CPC classification number: H01L21/32139 ,  H01L21/28123

Abstract: A patterning method allows for separate transfer of a complementary reticle set. In one embodiment, for example, the method includes etching a phase shift mask (PSM), then etching a cut mask for a cPSM mask. Moreover, a decoupled complementary mask patterning transfer method includes two separate and decoupled mask patterning steps which form combined patterns through the use of partial image transfers into an intermediate hard mask prior to final wafer patterning. The intermediate and final hard mask materials are chosen to prevent image transfer into an underlying substrate or wafer prior to the final etch process.

Abstract translation: 图案化方法允许互补掩模版集合的单独转移。 在一个实施例中，例如，该方法包括蚀刻相移掩模（PSM），然后蚀刻用于cPSM掩模的切割掩模。 此外，解耦互补掩模图案转移方法包括两个单独的和去耦的掩模图案化步骤，其通过在最终的晶片图案化之前通过使用部分图像转移到中间硬掩模中形成组合图案。 选择中间和最终硬掩模材料以防止在最终蚀刻工艺之前图像转移到下面的基底或晶片中。

公开(公告)号：US06586160B2

公开(公告)日：2003-07-01

申请号：US09817408

申请日：2001-03-26

Applicant: Chung-Peng Ho ,  Bernard J. Roman ,  Chong-Cheng Fu

Inventor： Chung-Peng Ho ,  Bernard J. Roman ,  Chong-Cheng Fu

IPC: G03F720

CPC classification number: G03F7/70333 ,  G03F7/70358

Abstract: A resist layer (34) on a semiconductor wafer (20) is patterned by using a scanning exposure system (50) which provides light, containing pattern information which is intended to be transferred to the wafer. The lithographic system is a step and scan system in which a reticle (16) passes between a light source and a lens system(18). The wafer with the resist layer is passed through a focal plane of the patterned light at a tilt angle (&thgr;). The user selects a desirable range for the depth of the resist to be exposed at the focus of the patterned light. The tilt angle is calculated by taking the arc tangent of the desirable range divided by a width of a slit region (52) of the projected light. The depth of focus increases over standard step and scan techniques.

公开(公告)号：US06168904A

公开(公告)日：2001-01-02

申请号：US08939422

申请日：1997-09-29

Applicant: John David Cuthbert ,  Chong-Cheng Fu

Inventor： John David Cuthbert ,  Chong-Cheng Fu

IPC: G03C500

CPC classification number: G03F7/70466 ,  G03F7/203

Abstract: An improved method of integrated circuit fabrication is described with a photolithographic step involving pattern decomposition. A desired final pattern is decomposed into two or more component patterns for photoresist imaging, leading to improvements in image fidelity.

Abstract translation: 通过涉及图案分解的光刻步骤描述了集成电路制造的改进方法。 期望的最终图案被分解成用于光致抗蚀剂成像的两个或更多个组件图案，导致图像保真度的改善。

公开(公告)号：US4519260A

公开(公告)日：1985-05-28

申请号：US574065

申请日：1984-01-26

Applicant: Chong-Cheng Fu ,  Levy Gerzberg

Inventor： Chong-Cheng Fu ,  Levy Gerzberg

IPC: G01F1/66 ,  G01P5/24 ,  G10K11/26 ,  G10K11/34

CPC classification number: G10K11/348 ,  G01F1/662 ,  G01P5/24 ,  G10K11/26

Abstract: Transducer structures for use in volume flow measurements which generate a first uniform beam and a second focused beam within the uniform beam. The transducer may include concentric elements, a linear array, or combinations thereof. In a two element concentric array, a central disc generates a uniform beam and a peripheral annular element having a lens thereon defines a second focused beam within the first beam. In a linear array a plurality of juxtaposed linear elements define a scan surface and a segmented element within the linear element array defines a focused reference sample volume within the scanned surface. A concentric array having a plurality of annular elements is driven with amplitude weighting of each element in accordance with a Fourier-Bessel approximation to the desired beam pattern thereby electronically achieving ultrasonic beam width control.

Abstract translation: 用于体积流量测量的传感器结构，其在均匀波束内产生第一均匀波束和第二聚焦光束。 换能器可以包括同心元件，线性阵列或其组合。 在两元件同心圆盘阵列中，中心盘产生均匀的光束，并且具有透镜的外围环形元件在第一光束内限定第二聚焦光束。 在线性阵列中，多个并置的线性元件限定了扫描表面，线性元件阵列内的分段元件限定了扫描表面内的聚焦参考样本体积。 具有多个环形元件的同心圆盘阵列根据对期望的波束图案的傅立叶 - 贝塞尔近似来驱动每个元件的振幅加权，从而电子地实现超声波束宽度控制。