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11.发明授权ESD protection snapback structure for overvoltage self-protecting I/O cells 有权过电压自保护I / O单元的ESD保护快速恢复结构公开(公告)号：US06952039B1
公开(公告)日：2005-10-04
申请号：US10656823
申请日：2003-09-04
CPC分类号： H01L27/0266 , H01L29/7835
摘要： In a self protection I/O, a multiple gate NMOS structure is designed to shift the avalanche multiplication region away from the edge of the gate nearest the drain. This is achieved by providing a lightly doped region between the edge of the gate and the ballast region of the drain.
摘要翻译： 在自保护I / O中，多栅极NMOS结构被设计成将雪崩倍增区域从距离漏极最近的栅极边缘移开。 这通过在栅极的边缘和漏极的镇流区之间提供轻掺杂区域来实现。
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公开(公告)号：US06933588B1
公开(公告)日：2005-08-23
申请号：US10134805
申请日：2002-04-29
IPC分类号： H01L27/02 , H01L27/06 , H01L29/732 , H01L27/082
CPC分类号： H01L27/0259 , H01L27/0623 , H01L29/7322 , Y10S257/918
摘要： In a NPN transistor electrostatic discharge (ESD) protection structure, certain parameters, including maximum lattice temperature, are improved by introducing certain process changes to provide for SCR-like characteristics during ESD events. A p+region is formed adjacent the collector to define a SCR-like emitter and with a common contact with the collector of the BJT. The p+ region is spaced from the n-emitter of the transistor by a n-epitaxial region, and the collector is preferably spaced further from the n-emitter than is the case in a regular BJT.
摘要翻译： 在NPN晶体管静电放电（ESD）保护结构中，通过引入特定的工艺变化来提供特定参数，包括最大晶格温度，以提供ESD事件期间的SCR样特性。 形成邻近集电极的p +区域，以限定SCR类发射极，并与BJT的集电极共同接触。 p +区域通过n外延区域与晶体管的n发射极间隔开，并且与常规BJT的情况相比，集电极优选与n发射极隔开。
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13.发明授权公开(公告)号：US07193251B1
公开(公告)日：2007-03-20
申请号：US10339192
申请日：2003-01-09
IPC分类号： H01L29/74
CPC分类号： H01L27/0262
摘要： In multiple port chip circuit, an ESD protection circuit and method of protecting the ports of the multiple port circuit, includes providing a plurality of bi-directional snapback devices such as DIACs and connecting only one electrode to ground while connecting the other electrodes to the ports that are to be protected.
摘要翻译： 在多端口芯片电路中，ESD保护电路和保护多端口电路端口的方法包括：提供多个双向快速恢复装置，例如DIAC，并且仅将一个电极连接到地，同时将其它电极连接到端口 那些被保护。
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公开(公告)号：US07057215B1
公开(公告)日：2006-06-06
申请号：US10210948
申请日：2002-08-02
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L27/0266 , H01L29/87
摘要： In an ESD protection device making use of a LVTSCR-like structure or an IGBT-like structure, negative polarity over-voltage protection is achieved by providing a LVTSCR-like structure or IGBT-like structure that defines a PMOS device.
摘要翻译： 在使用LVTSCR结构或类IGBT结构的ESD保护器件中，通过提供限定PMOS器件的类似LVTSCR的结构或类IGBT结构来实现负极性过电压保护。
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公开(公告)号：US06841829B1
公开(公告)日：2005-01-11
申请号：US10436559
申请日：2003-05-12
IPC分类号： H01L27/02 , H01L29/06 , H01L29/732 , H01L23/62 , H01L29/00
CPC分类号： H01L29/732 , H01L27/0262 , H01L29/0692 , H01L29/0821
摘要： In a BSCR and method of making a BSCR, a npn BJT structure is created and a p+ region is provided that is connected to the collector of the BJT, and one or more of the NBL, sinker and n+ collector of the BJT are partially blocked. In this way the NBL is formed into a comb-like NBL with a plurality of tines in one embodiment. The sinker and n+ collector may also be formed into a plurality islands. Furthermore, the period of the tines and islands may be varied to provide the desired BSCR characteristics.
摘要翻译： 在BSCR和制造BSCR的方法中，产生npn BJT结构，并且提供连接到BJT的集电极的p +区域，并且BJT的NBL，沉没器和n +集电极中的一个或多个被部分阻塞 。 以这种方式，在一个实施例中，NBL形成为具有多个尖齿的梳状NBL。 沉降片和n +集电体也可形成多个岛。 此外，可以改变尖齿和岛的周期以提供期望的BSCR特性。
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公开(公告)号：US06784029B1
公开(公告)日：2004-08-31
申请号：US10121514
申请日：2002-04-12
IPC分类号： H01L218248
CPC分类号： H01L27/0262 , H01L27/0623 , H01L29/0626 , H01L29/0649 , H01L29/87
摘要： In a Bi-CMOS ESD protection device, dual voltage capabilities are achieved by providing two laterally spaced p-regions in a n-material and defining a n+ region and a p+ region in each of the p-regions to define I-V characteristics that are similar to those defined by a SCR device in a positive direction, but, in this case, having those characteristics in both directions. The device may be asymmetrical to accommodate different voltage amplitudes in the positive and negative directions.
摘要翻译： 在Bi-CMOS ESD保护器件中，通过在n型材料中提供两个横向间隔开的p区并且在每个p区中限定n +区和p +区以实现类似的IV特性来实现双电压能力。 对于由SCR装置在正方向上限定的那些，但是在这种情况下，在两个方向具有这些特性。 器件可能是不对称的，以适应正向和负向不同的电压幅度。
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17.发明授权公开(公告)号：US06717219B1
公开(公告)日：2004-04-06
申请号：US10121183
申请日：2002-04-12
IPC分类号： H01L2362
CPC分类号： H01L29/7436 , H01L27/0259
摘要： In a Bi-CM0S ESD protection structure, the holding voltage is increased by a desired amount by including a NBL of chosen length. The positioning of the NBL may be adjusted to adjust the I-V characteristics of the structure. Dual voltage capabilities may be achieved by providing two laterally spaced p-regions in a n-material and defining a n+ region and a p+ region in each of the p-regions to define I-V characteristics that are similar to those defined by a SCR device in a positive direction, but, in this case, having those characteristics in both directions. Over and above the NBL position being adjusted relative to the p-regions, the two p-regions may vary in doping level, and dimensions to achieve different I-V characteristics for the device in the positive and negative directions.
摘要翻译： 在Bi-CM0S ESD保护结构中，通过包括选定长度的NBL，保持电压增加所需量。 可以调整NBL的定位以调整结构的I-V特性。 可以通过在n材料中提供两个横向间隔的p区并且在每个p区中限定n +区和p +区来限定IV特性来实现双电压能力，其类似于由SCR器件中定义的那些 正方向，但是在这种情况下，在两个方向都具有这些特征。 在相对于p区域调整NBL位置之上和之上时，两个p区可以在掺杂水平和尺寸上变化，以在正向和负向方向上实现器件的不同I-V特性。
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公开(公告)号：US06690069B1
公开(公告)日：2004-02-10
申请号：US10210941
申请日：2002-08-02
IPC分类号： H01L2362
CPC分类号： H01L27/0262
摘要： In an ESD protection device using a SCR-like structure, a vertical device is provided that is highly robust and easily allows the triggering voltage to be adjusted during manufacture. Furthermore it is implementable in complementary form based on PNP and NPN BJT structures, to provide both positive and negative pulse protection.
摘要翻译： 在使用SCR类结构的ESD保护器件中，提供了高度鲁棒的垂直器件，并且容易地允许在制造期间调节触发电压。 此外，它可以基于PNP和NPN BJT结构的互补形式实现，以提供正和负脉冲保护。
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公开(公告)号：US07056761B1
公开(公告)日：2006-06-06
申请号：US10388815
申请日：2003-03-14
CPC分类号： H01L29/7391 , H01L29/866 , Y10S438/979 , Y10S438/983
摘要： In an avalanche structure, different breakdown voltages are achieved by making use of a polygate and forming a highly doped p-n junction beneath the polygate, and adjusting the gate length and optionally the bias voltage of the gate.
摘要翻译： 在雪崩结构中，通过利用多晶硅栅极形成不同的击穿电压，并在多晶硅管下面形成高掺杂的p-n结，并调整栅极长度和可选的栅极偏置电压。
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公开(公告)号：US06822294B1
公开(公告)日：2004-11-23
申请号：US09896681
申请日：2001-06-29
IPC分类号： H01L2362
CPC分类号： H01L27/0262 , H01L29/87
摘要： In an ESD protection device using a LVTSCR-like structure, the holding voltage is increased by placing the p+ emitter outside the drain of the device, thereby retarding the injection of holes from the p+ emitter. The p+ emitter may be implemented in one or more emitter regions formed outside the drain. The drain is split between a n+ drain and a floating n+ region near the gate to avoid excessive avalanche injection and resultant local overheating.
摘要翻译： 在使用类似LVTSCR的结构的ESD保护器件中，通过将p +发射极放置在器件的漏极之外，从而延长了p +发射极的空穴注入，从而提高了保持电压。 p +发射极可以在形成在漏极外部的一个或多个发射极区域中实现。 漏极在栅极附近的n +漏极和浮动n +区域之间分开，以避免过度的雪崩注入和局部过热。
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