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11.发明授权Oversampling analog-to-digital converter with improved DC offset performance 有权具有改进的直流偏移性能的过采样模数转换器公开(公告)号：US06411242B1
公开(公告)日：2002-06-25
申请号：US09593021
申请日：2000-06-13
IPC分类号： H03M112
CPC分类号： H03M1/0663 , H03M1/12 , H03M3/34 , H03M3/424 , H03M3/464
摘要： The invention provides methods and apparatus for improving the direct current (DC) offset performance of an oversampling analog-to-digital (A/D) converter, including A/D converters that include an oversampling quantizer such as a single or multi-bit &Dgr;-&Sgr; modulator, successive approximation quantizer, flash quantizer, pipelined quantizer or other suitable oversampling quantizer. The invention also relates to methods for providing a wide-band attenuation in the digital output of an A/D converter using a limited number of components.
摘要翻译： 本发明提供了用于改进过采样模数（A / D）转换器的直流（DC）偏移性能的方法和装置，包括A / D转换器，其包括过采样量化器，例如单位或多位DELTA -SIGMA调制器，逐次逼近量化器，闪光量化器，流水线量化器或其它合适的过采样量化器。 本发明还涉及使用有限数量的组件在A / D转换器的数字输出中提供宽带衰减的方法。
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公开(公告)号：US06169506A
公开(公告)日：2001-01-02
申请号：US09135161
申请日：1998-08-17
IPC分类号： H03M300
摘要： An oversampling data converter with good rejection capability is provided. The oversampling data converter includes three primary parts; a delta-sigma modulator for sampling and digitizing incoming analog signals, a high order digital filter for discarding unwanted frequency components, and an internal clock generator for controlling the operation of the modulator and the filter. All three primary parts are provided in the same package and also on the same die. No frequency-setting external components are necessary. The high order digital filter provides more than 100 dB rejection at a first null frequency. The first null provided by the filter has a sufficiently broad range so as to allow a low accuracy internal clock generator to be used. If necessary, the clock can be generated externally or from some other part of the system.
摘要翻译： 提供了具有良好抑制能力的过采样数据转换器。 过采样数据转换器包括三个主要部分; 用于对输入模拟信号进行采样和数字化的Δ-Σ调制器，用于丢弃不需要的频率分量的高阶数字滤波器，以及用于控制调制器和滤波器的操作的内部时钟发生器。 所有三个主要部件都提供在相同的包装中，并且在同一个模具上。 不需要频率设置外部组件。 高阶数字滤波器在第一个零频率处提供超过100 dB的抑制。 由滤波器提供的第一个零点具有足够宽的范围，以便允许使用低精度的内部时钟发生器。 如果需要，时钟可以从外部或从系统的其他部分生成。
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公开(公告)号：US5396245A
公开(公告)日：1995-03-07
申请号：US7108
申请日：1993-01-21
申请人： William C. Rempfer
发明人： William C. Rempfer
CPC分类号： H03M1/682 , H03F3/45479 , H03M1/0602 , H03M1/1061 , H03F2203/45358 , H03F2203/7215 , H03F2203/7236 , H03M1/0682 , H03M1/687 , H03M1/747 , H03M1/765
摘要： A segmented DAC is described in which the outputs of a pair of subword DAC circuits are summed by modulating the offset voltage of a differential buffer amplifier. Also described are various alternative DAC embodiments and an operational amplifier input stage in which modulation of the offset voltage of a differential amplifier responsive to a digital signal is accomplished using interpolation techniques for eliminating errors in linearity and monotonicity arising from component inaccuracies.
摘要翻译： 描述了分段DAC，其中一对子字DAC电路的输出通过调制差分缓冲放大器的偏移电压而相加。 还描述了各种替代DAC实施例和运算放大器输入级，其中使用插值技术来实现响应于数字信号的差分放大器的偏移电压的调制，以消除由分量不准确性引起的线性和单调性的误差。
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