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1.发明授权Oversampling analog-to-digital converter with improved DC offset performance 有权具有改进的直流偏移性能的过采样模数转换器公开(公告)号：US06411242B1
公开(公告)日：2002-06-25
申请号：US09593021
申请日：2000-06-13
IPC分类号： H03M112
CPC分类号： H03M1/0663 , H03M1/12 , H03M3/34 , H03M3/424 , H03M3/464
摘要： The invention provides methods and apparatus for improving the direct current (DC) offset performance of an oversampling analog-to-digital (A/D) converter, including A/D converters that include an oversampling quantizer such as a single or multi-bit &Dgr;-&Sgr; modulator, successive approximation quantizer, flash quantizer, pipelined quantizer or other suitable oversampling quantizer. The invention also relates to methods for providing a wide-band attenuation in the digital output of an A/D converter using a limited number of components.
摘要翻译： 本发明提供了用于改进过采样模数（A / D）转换器的直流（DC）偏移性能的方法和装置，包括A / D转换器，其包括过采样量化器，例如单位或多位DELTA -SIGMA调制器，逐次逼近量化器，闪光量化器，流水线量化器或其它合适的过采样量化器。 本发明还涉及使用有限数量的组件在A / D转换器的数字输出中提供宽带衰减的方法。
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公开(公告)号：US06169506A
公开(公告)日：2001-01-02
申请号：US09135161
申请日：1998-08-17
IPC分类号： H03M300
摘要： An oversampling data converter with good rejection capability is provided. The oversampling data converter includes three primary parts; a delta-sigma modulator for sampling and digitizing incoming analog signals, a high order digital filter for discarding unwanted frequency components, and an internal clock generator for controlling the operation of the modulator and the filter. All three primary parts are provided in the same package and also on the same die. No frequency-setting external components are necessary. The high order digital filter provides more than 100 dB rejection at a first null frequency. The first null provided by the filter has a sufficiently broad range so as to allow a low accuracy internal clock generator to be used. If necessary, the clock can be generated externally or from some other part of the system.
摘要翻译： 提供了具有良好抑制能力的过采样数据转换器。 过采样数据转换器包括三个主要部分; 用于对输入模拟信号进行采样和数字化的Δ-Σ调制器，用于丢弃不需要的频率分量的高阶数字滤波器，以及用于控制调制器和滤波器的操作的内部时钟发生器。 所有三个主要部件都提供在相同的包装中，并且在同一个模具上。 不需要频率设置外部组件。 高阶数字滤波器在第一个零频率处提供超过100 dB的抑制。 由滤波器提供的第一个零点具有足够宽的范围，以便允许使用低精度的内部时钟发生器。 如果需要，时钟可以从外部或从系统的其他部分生成。
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公开(公告)号：US5287525A
公开(公告)日：1994-02-15
申请号：US10477
申请日：1993-01-28
申请人： Sammy S. Lum , William C. Rempfer
发明人： Sammy S. Lum , William C. Rempfer
CPC分类号： G06F1/3246 , G06F1/3203
摘要： Power shutdown of an integrated circuit such as a data acquisition system is implemented by software command. In one embodiment of a data acquisition system, an 8 bit data input word for configuring the operation of the data acquisition system includes two word length bits which define the length of data output words. One combination of the word length bits is utilized to command power shutdown. A decoder within the integrated circuit identifies the power shutdown command and generates a power shutdown signal (PS) to minimize power consumption when the circuit is not in operation.
摘要翻译： 通过软件命令实现数据采集系统等集成电路的电源关闭。 在数据采集系统的一个实施例中，用于配置数据采集系统的操作的8位数据输入字包括限定数据输出字长度的两个字长比特位。 字长比特的一个组合被用于指令关机。 集成电路内的解码器识别电源关闭命令并产生电源关闭信号（PS），以在电路不工作时最小化功耗。
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4.发明授权Bidirectional shift register using parallel inverters with adjustable transconductance 失效具有可调跨导的并联逆变器的双向移位寄存器
公开(公告)号：US4624006A
公开(公告)日：1986-11-18
申请号：US732660
申请日：1985-05-10
IPC分类号： G11C19/28
CPC分类号： G11C19/28
摘要： A bidirectional shift register includes a plurality of serially connected cells with each cell having a first circuit portion and a second circuit portion. Each circuit portion includes at least two parallel inverters connected in opposite directions. The relative transconductance of the oppositely connected inverters in each circuit portion of a cell can be varied thereby determining the direction of data flow through the circuit portion and through the bidirectional shift register.
摘要翻译： 双向移位寄存器包括多个串行连接的单元，每个单元具有第一电路部分和第二电路部分。 每个电路部分包括沿相反方向连接的至少两个并联逆变器。 可以改变单元的每个电路部分中的相反连接的反相器的相对跨导，从而确定通过电路部分和通过双向移位寄存器的数据流的方向。
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5.发明授权Circuits and methods for compensating non-linear capacitances to minimize harmonic distortion 失效用于补偿非线性电容以最小化谐波失真的电路和方法
公开(公告)号：US5763924A
公开(公告)日：1998-06-09
申请号：US647361
申请日：1996-05-09
申请人： Sammy S. Lum , William C. Rempfer
发明人： Sammy S. Lum , William C. Rempfer
IPC分类号： G11C27/02 , H01L27/06 , H01L27/092 , H01L29/76 , H01L29/74
CPC分类号： G11C27/02 , G11C27/024 , H01L27/0629 , H01L27/092
摘要： A simple, low-cost circuit and method for line zing parasitic capacitances of transistor junctions, independent of the process technology employed, are provided. In the preferred embodiment, the parasitic capacitance of a transistor in a track and hold circuit is linearized by providing a pair of diodes that act inversely to the parasitic diodes formed within the integrated circuit during normal tracking operations. Without the diodes of the present invention, the varying input signals cause the parasitic capacitance to vary, thereby causing harmonic distortion in the track and hold circuit. An alternate embodiment of the present invention is also provided in which a second complementary transistor is provided. The inclusion of the complementary transistor results in a second set of parasitic capacitances that are substantially opposite the parasitic capacitances of the track and hold transistor. Additionally, depending on the ratios of the various components, the techniques of the two embodiments may be, combined, such that additional diode may be added even if the complementary transistor technique is utilized.
摘要翻译： 提供了一种简单，低成本的电路和方法，用于管线晶体管结的寄生电容，与所采用的工艺技术无关。 在优选实施例中，轨道和保持电路中的晶体管的寄生电容通过在正常跟踪操作期间提供与形成在集成电路内的寄生二极管相反的一对二极管来线性化。 如果没有本发明的二极管，变化的输入信号会引起寄生电容的变化，从而导致轨道和保持电路中的谐波失真。 还提供了本发明的替代实施例，其中提供第二互补晶体管。 包含互补晶体管产生与轨道和保持晶体管的寄生电容基本相反的第二组寄生电容。 另外，根据各种组件的比例，两个实施例的技术可以组合起来使得即使利用互补晶体管技术也可以添加额外的二极管。
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公开(公告)号：US5212618A
公开(公告)日：1993-05-18
申请号：US518151
申请日：1990-05-03
IPC分类号： H01L27/02
CPC分类号： H01L27/0248
摘要： An electrostatic discharge protection clamp particularly useful for with bipolar and biCMOS integrated circuits include an NPN transistor formed in an isolated tub in an epitaxial layer grown on a substrate. The collector of the NPN transistor is connected to the input terminal, and the emitter of the NPN transistor is connected to the substrate. A resistor interconnects the base and the emitter. Advantageously, the P-doped base can abut the P-doped isolation region forming the tub, and the P-doped isolation region can interconnect the emitter to the substrate. Below BV.sub.CES the clamp will look like an open circuit, and above BV.sub.CES the transistor will start conducting current. The transistor will break down collector to base. Conduction of the transistor causes a voltage drop across the base-emitter junction, and when this voltage drop exceeds the base-emitter forward voltage the transistor will turn on. Once the transistor is turned on and current starts flowing in the emitter, avalanche effects will cause the breakdown voltage to snap back to BV.sub.CEO and remain there until the emitter current drops below some low level, which will be at the end of the electrostatic discharge pulse. In the negative direction the tub to substrate diode provides an effective clamp which will clamp the voltage to a low value and limit the power dissipation in the junction. Alternatively, a bidirectional clamp can be provided in which a second NPN transistor is fabricated in the tub with the emitter of the second transistor connected to the input terminal and the collectors of the two transistors being interconnected by the N-doped epitaxial layer of the tub. The dopant conductivities can be reversed.
摘要翻译： 特别适用于双极和biCMOS集成电路的静电放电保护钳包括形成在衬底上生长的外延层中的隔离桶中的NPN晶体管。 NPN晶体管的集电极连接到输入端子，NPN晶体管的发射极连接到基板。 电阻器将基极和发射极互连。 有利地，P掺杂的基极可以邻接形成桶的P掺杂隔离区，并且P掺杂隔离区可以将发射极与衬底互连。 在BVCES下方，钳位将看起来像一个开路，而在BVCES之上，晶体管将开始导通电流。 晶体管会将集电极分解为基极。 晶体管的导通导致基极 - 发射极结两端的电压降，当该电压降超过基极 - 发射极正向电压时，晶体管将导通。 一旦晶体管导通并且电流开始在发射极中流动，雪崩效应将导致击穿电压反弹至BVCEO，并保持在那里，直到发射极电流下降到一些低电平，这将在静电放电脉冲结束时 。 在负向方向上，桶至衬底二极管提供有效钳位，其将电压钳位到低值并限制结中的功率耗散。 或者，可以提供双向钳位，其中第二NPN晶体管制造在桶中，其中第二晶体管的发射极连接到输入端，并且两个晶体管的集电极通过盆的N掺杂外延层互连 。 掺杂剂的电导率可以颠倒。
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公开(公告)号：US06937178B1
公开(公告)日：2005-08-30
申请号：US10440080
申请日：2003-05-15
CPC分类号： H03M1/0678 , H03M1/0643 , H03M1/765
摘要： Digital to analog converter circuits and methods are provided for producing an analog output voltage indicative of a digital input signal with at least partial insensitivity to error gradients. Described are split-core resistive elements, which include a plurality of one-dimensional or multi-dimensional resistive strings, that may be used to reduce or substantially eliminate the effects that error gradients have on the linearity of the analog output voltages of a resistive string or interpolating amplifier DACs. The resistor strings that make up the split-core resistive elements are configured in such a manner that combining respective output voltages from each of the resistor strings results in an analog output voltage that is at least partially insensitive to the effects of error gradients.
摘要翻译： 提供数模转换器电路和方法用于产生表示对错误梯度至少部分不敏感的数字输入信号的模拟输出电压。 描述的是分离电阻元件，其包括多个一维或多维电阻串，其可用于减少或基本上消除误差梯度对电阻串的模拟输出电压的线性的影响 或内插放大器DAC。 构成分离电阻元件的电阻串以这样的方式配置，即组合来自每个电阻器串的各个输出电压导致对误差梯度的影响至少部分不敏感的模拟输出电压。
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8.发明授权Programmable configuration, level and output voltage range circuits and methods for signal processors 有权信号处理器的可编程配置，电平和输出电压范围电路和方法公开(公告)号：US06310567B1
公开(公告)日：2001-10-30
申请号：US09390178
申请日：1999-09-07
IPC分类号： H03M118
CPC分类号： H03M1/66
摘要： A signal processor circuit which receives an input signal and two control words and is programmable to vary the level and the output voltage range of the output signal is provided. The signal processor includes a converter circuit and a level circuit which provide the output circuit with intermediate signals based on input control signals, e.g., input digital words. The output circuit receives an additional control signal and the intermediate signals and is programmable to modify the output voltage range and level of the output signal based on the additional control signal, e.g., a digital word.
摘要翻译： 提供一种接收输入信号和两个控制字并且被编程以改变输出信号的电平和输出电压范围的信号处理器电路。 信号处理器包括转换器电路和电平电路，其基于诸如输入数字字的输入控制信号为输出电路提供中间信号。 输出电路接收附加控制信号和中间信号并且可编程以基于附加控制信号（例如数字字）来修改输出电压范围和输出信号的电平。
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公开(公告)号：US5714955A
公开(公告)日：1998-02-03
申请号：US486862
申请日：1995-06-07
摘要： Serial analog-to-digital converters (ADC) in which power down and power up modes are activated by two dual-purpose input signals are provided. The ADCs of the invention eliminate the need for a dedicated power down input line as found on typical serial ADCs. When commanded to do so, the ADC enters into one of two power down modes, NAP or SLEEP. In NAP mode, only those portions of the ADC circuit which consume current and which are capable of waking up almost instantaneously are powered down. In SLEEP mode, the entire ADC circuit is powered down. When commanded to do so, the ADC enters into a power up mode, applying current to every portion of the ADC circuit. Wake-up from the NAP mode takes place almost instantaneously. Wake-up from the SLEEP mode requires additional time. From either mode, a signal is generated when the ADC conversion circuit, which preferably includes a reference voltage generator, has stabilized sufficiently for the ADC to perform analog-to-digital conversion.
摘要翻译： 提供了通过两个双用途输入信号激活掉电和上电模式的串行模数转换器（ADC）。 本发明的ADC消除了对典型串行ADC所发现的专用掉电输入线的需要。 当指令这样做时，ADC进入两种掉电模式之一NAP或SLEEP。 在NAP模式下，只有那些消耗电流且几乎瞬间唤醒的ADC电路的那些部分掉电。 在休眠模式下，整个ADC电路掉电。 当指令这样做时，ADC进入上电模式，将电流施加到ADC电路的每个部分。 从NAP模式唤醒几乎瞬间发生。 从休眠模式唤醒需要额外的时间。 在任一模式下，当ADC转换电路（其优选地包括参考电压发生器）已经足够稳定以使ADC执行模数转换时产生信号。
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10.发明授权Circuits, systems, and methods for signal processors that buffer a signal dependent current 有权用于缓冲信号相关电流的信号处理器的电路，系统和方法公开(公告)号：US06492924B2
公开(公告)日：2002-12-10
申请号：US09932518
申请日：2001-08-17
IPC分类号： H03M188
CPC分类号： H03M1/66
摘要： A signal processor circuit that buffers a ground-referred, signal-dependent, current. A ground-referred node in the circuit is preferably maintained at a ground level. The ground-referred, signal-dependent, current is preferably buffered such that the ground-referred node is preferably maintained at a ground level independent of changes to the ground-referred, signal-dependent, current.
摘要翻译： 一种信号处理器电路，用于缓冲接地参考信号相关电流。 电路中的接地参考节点优选地保持在地平面。 地面参考的信号相关电流优选地被缓冲，使得接地参考节点优选地保持在接地电平，而不依赖于对地面参考的信号相关电流的改变。
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