公开(公告)号：US08629705B2

公开(公告)日：2014-01-14

申请号：US12794995

申请日：2010-06-07

申请人： Leland Chang ,  Robert H. Dennard ,  Brian L. Ji ,  Wing K. Luk ,  Robert K. Montoye

发明人： Leland Chang ,  Robert H. Dennard ,  Brian L. Ji ,  Wing K. Luk ,  Robert K. Montoye

IPC分类号： H03L5/00

CPC分类号： H02M3/07 ,  H02M2003/072

摘要： A low voltage signaling system for integrated circuits includes a first voltage domain operating at a nominal integrated circuit (IC) power supply voltage (Vdd) swing level at a signal transmitting end of a first chip, a second voltage domain having one or more transmission interconnect lines operating at a reduced voltage swing level with respect to the first voltage domain, and a third voltage domain at a signal receiving end of a second chip, the third voltage domain operating at the Vdd swing level; wherein an input signal originating from the first voltage domain is down converted to operate at the reduced voltage swing level for transmission over the second voltage domain, and wherein the third voltage domain senses the input signal transmitted over the second voltage domain and generates an output signal operating back up at the Vdd swing level.

摘要翻译： 用于集成电路的低电压信号系统包括在第一芯片的信号发射端处以标称集成电路（IC）电源电压（Vdd）摆幅电平操作的第一电压域，具有一个或多个传输互连的第二电压域 以相对于第一电压域的降低的电压摆动电平工作的线路，以及在第二芯片的信号接收端的第三电压域，以Vdd摆动电平工作的第三电压域; 其中源自所述第一电压域的输入信号被降频转换以在所述降低的电压摆幅电平下工作以在所述第二电压域上传输，并且其中所述第三电压域检测在所述第二电压域上传输的输入信号，并产生输出信号 以Vdd摆动水平运行。

公开(公告)号：US08314380B2

公开(公告)日：2012-11-20

申请号：US12558026

申请日：2009-09-11

申请人： John E. Breeding ,  William F. Jones ,  Wing K. Luk ,  Andrew P. Moor ,  Johnny H. Reed ,  David Townsend

发明人： John E. Breeding ,  William F. Jones ,  Wing K. Luk ,  Andrew P. Moor ,  Johnny H. Reed ,  David Townsend

IPC分类号： H01J49/00 ,  G01T1/161

CPC分类号： G06T11/005

摘要： A patient bed drive mechanism, under control of a processor, is capable of continuously moving a patient bed through the a TOF-PET detector array having a stationary field of view (FOV) for a distance in excess of the physical extent of an axis of the array FOV. A direct memory access (DMA) rebinner card is coupled to the detector array to receive therefrom a stream of TOF-PET coincidence event data during the extent of movement of the bed. Image projection data are generated in real time from the acquired stream of TOF-PET coincidence event data via the DMA card.

摘要翻译： 在处理器的控制下，患者床驱动机构能够通过具有静止视野（FOV）的TOF-PET检测器阵列连续地移动患者床，距离超过轴的物理范围 阵列FOV。 直接存储器访问（DMA）重组卡耦合到检测器阵列以在床的移动范围内从其接收TOF-PET重合事件数据流。 图像投影数据通过DMA卡从所获取的TOF-PET符合事件数据流中实时生成。

公开(公告)号：US08120386B2

公开(公告)日：2012-02-21

申请号：US12542793

申请日：2009-08-18

申请人： Wing K. Luk ,  Robert H. Dennard

发明人： Wing K. Luk ,  Robert H. Dennard

IPC分类号： G11C7/08 ,  H03F11/00 ,  H03K5/24

CPC分类号： H03F1/56 ,  G11C7/06 ,  H01L27/0811 ,  H01L29/7391 ,  H03F2200/183

摘要： A circuit comprises a control line and a two terminal semiconductor device having first and second terminals. The first terminal is coupled to a signal line, and the second terminal is coupled to the control line. The two terminal semiconductor device is adapted to have a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and to have a smaller capacitance when a voltage on the first terminal relative to the second terminal is below the threshold voltage. The control line is coupled to a control signal and the signal line is coupled to a signal and is output of the circuit. A signal is placed on the signal line and voltage on the control line is modified (e.g., raised in the case of n-type devices, or lowered for a p-type devices). When the signal falls below the threshold voltage, the two terminal semiconductor device acts as a very small capacitor and the output of the circuit will be a small value. When the signal is above the threshold voltage, the two terminal semiconductor device acts as a large capacitor and the output of the circuit will be influenced by both the value of the signal and the value of the modified voltage on the control line and therefore the signal will be amplified.

摘要翻译： 电路包括控制线和具有第一和第二端子的两端子半导体器件。 第一端子耦合到信号线，并且第二端子耦合到控制线。 当第一端子上相对于第二端子的电压高于阈值电压时，两端子半导体器件适于具有电容，并且当第一端子上相对于第二端子的电压低于阈值时具有较小的电容 电压。 控制线耦合到控制信号，并且信号线耦合到信号并且是电路的输出。 将信号放置在信号线上，并且控制线上的电压被修改（例如在n型器件的情况下升高，或者对于p型器件降低）。 当信号低于阈值电压时，两端子半导体器件作为一个非常小的电容器，并且电路的输出将是一个小的值。 当信号高于阈值电压时，两端子半导体器件用作大电容器，电路的输出将受到信号值和控制线上修改电压值的影响，因此信号 将被放大。

公开(公告)号：US20090302936A1

公开(公告)日：2009-12-10

申请号：US12542793

申请日：2009-08-18

申请人： Wing K. Luk ,  Robert H. Dennard

发明人： Wing K. Luk ,  Robert H. Dennard

IPC分类号： H03F11/00

CPC分类号： H03F1/56 ,  G11C7/06 ,  H01L27/0811 ,  H01L29/7391 ,  H03F2200/183

摘要： A circuit comprises a control line and a two terminal semiconductor device having first and second terminals. The first terminal is coupled to a signal line, and the second terminal is coupled to the control line. The two terminal semiconductor device is adapted to have a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and to have a smaller capacitance when a voltage on the first terminal relative to the second terminal is below the threshold voltage. The control line is coupled to a control signal and the signal line is coupled to a signal and is output of the circuit. A signal is placed on the signal line and voltage on the control line is modified (e.g., raised in the case of n-type devices, or lowered for a p-type devices). When the signal falls below the threshold voltage, the two terminal semiconductor device acts as a very small capacitor and the output of the circuit will be a small value. When the signal is above the threshold voltage, the two terminal semiconductor device acts as a large capacitor and the output of the circuit will be influenced by both the value of the signal and the value of the modified voltage on the control line and therefore the signal will be amplified.

摘要翻译： 电路包括控制线和具有第一和第二端子的两端子半导体器件。 第一端子耦合到信号线，并且第二端子耦合到控制线。 当第一端子上相对于第二端子的电压高于阈值电压时，两端子半导体器件适于具有电容，并且当第一端子上相对于第二端子的电压低于阈值时具有较小的电容 电压。 控制线耦合到控制信号，并且信号线耦合到信号并且是电路的输出。 将信号放置在信号线上，并且控制线上的电压被修改（例如在n型器件的情况下升高，或者对于p型器件降低）。 当信号低于阈值电压时，两端子半导体器件作为一个非常小的电容器，并且电路的输出将是一个小的值。 当信号高于阈值电压时，两端子半导体器件用作大电容器，电路的输出将受到信号值和控制线上修改电压值的影响，因此信号 将被放大。

公开(公告)号：US20090059653A1

公开(公告)日：2009-03-05

申请号：US12266650

申请日：2008-11-07

申请人： Wing K. Luk ,  Brian L. Ji

发明人： Wing K. Luk ,  Brian L. Ji

IPC分类号： G11C11/24 ,  G11C7/06 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C8/16 ,  G11C11/403 ,  G11C11/405 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2211/4065

摘要： A dynamic random access memory circuit is provided, having at least one write bit line, at least one read bit line, a capacitive storage device, a write access device operatively coupled to the capacitive storage device and the at least one write bit line, a sense amplifier operatively coupled to the at least one read bit line and configured to generate an output signal, a refresh bypass device operatively associated with the sense amplifier and the at least one write bit line so as to selectively pass the output signal to the at least one write bit line, and a write-read bypass device operatively coupled to the at least one write bit line and the at least one read bit line and configured to selectively pass a write signal from a write bit line signal point along the at least one write bit line to a read bit line signal point along the at least one read bit line for output to a data output. the output signal is selectively passed to the at least one write bit line. The write signal is selectively passed from the write bit line signal point along the at least one write bit line to the read bit line signal point along the at least one read bit line for output to the data output.

摘要翻译： 提供了一种动态随机存取存储器电路，其具有至少一个写位线，至少一个读位线，电容存储器件，可操作地耦合到电容存储器件和至少一个写位线的写入存取器件， 感测放大器，其可操作地耦合到所述至少一个读取位线并且被配置为产生输出信号，与所述读出放大器和所述至少一个写位线可操作地相关联的刷新旁路装置，以选择性地将所述输出信号传递到所述至少一个 一个写入位线以及可操作地耦合到所述至少一个写入位线和所述至少一个读取位线的写入读取旁路器件，并被配置为沿着所述至少一个读取位线选择性地传递来自写入位线信号点的写入信号 将位线沿着至少一个读位线写入读位线信号点，以输出到数据输出。 输出信号被选择性地传递到至少一个写位线。 写入信号从写入位线信号点沿着至少一个写位线选择性地沿着至少一个读位线传递到读位线信号点，以输出到数据输出端。

公开(公告)号：US20080195887A1

公开(公告)日：2008-08-14

申请号：US11673657

申请日：2007-02-12

申请人： Wing K. Luk ,  Ravi Nair

发明人： Wing K. Luk ,  Ravi Nair

IPC分类号： G06F11/00 ,  G06F12/00

CPC分类号： G06F12/0893 ,  G06F11/1064 ,  G06F12/0891 ,  G11C7/1006 ,  G11C2029/0411 ,  G11C2207/2245 ,  Y02D10/13

摘要： Embodiments include a DRAM cache structure, associated circuits and method of operations suitable for use with high-speed caches. The DRAM caches do not require regular refresh of its data and hence the refresh blank-out period and refresh power are eliminated, thus improving cache availability and reducing power compared to conventional DRAM caches. Compared to existing SRAM caches, the new cache structures can potentially achieve the same (or better) speed, lower power and better tolerance to chip process variations in future process technologies.

摘要翻译： 实施例包括DRAM高速缓存结构，相关联的电路以及适用于高速缓存的操作方法。 DRAM高速缓存不需要定期刷新其数据，因此消除了刷新空白期和刷新功率，从而与常规DRAM高速缓存相比提高了高速缓存可用性和降低功耗。 与现有的SRAM高速缓存相比，新的高速缓存结构可能在未来的工艺技术中潜在地实现相同（或更好）的速度，更低的功耗和更好的对芯片工艺变化的容限。

公开(公告)号：US5392221A

公开(公告)日：1995-02-21

申请号：US714027

申请日：1991-06-12

申请人： Wilm E. Donath ,  Wing K. Luk ,  Donald T. Tang

发明人： Wilm E. Donath ,  Wing K. Luk ,  Donald T. Tang

IPC分类号： H01L21/82 ,  G06F17/50 ,  H03K19/0185 ,  G06F15/60

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： A method and apparatus for minimizing the total power of a logic network subject to timing constraints. The method describes a procedure to assign power and/or delay to each circuit in a logic network such that the total power is minimized and the arrival time requirement at the outputs of the logic network is met. A subset of circuits in the logic network are powered up and powered down in repeated succession in order to minimize the total power of the logic network.

摘要翻译： 一种用于使经受时序约束的逻辑网络的总功率最小化的方法和装置。 该方法描述了对逻辑网络中的每个电路分配功率和/或延迟的过程，使得总功率被最小化并且满足逻辑网络的输出处的到达时间要求。 逻辑网络中的电路子集被重新连续上电和断电，以便最小化逻辑网络的总功率。

公开(公告)号：US07941728B2

公开(公告)日：2011-05-10

申请号：US11683285

申请日：2007-03-07

申请人： Philip George Emma ,  Wing K. Luk ,  Thomas R. Puzak ,  Vijayalakshmi Srinivasan

发明人： Philip George Emma ,  Wing K. Luk ,  Thomas R. Puzak ,  Vijayalakshmi Srinivasan

IPC分类号： H03M13/00

CPC分类号： G06F12/0802 ,  G06F11/1064 ,  G06F11/1666

摘要： A system and method of providing a cache system having a store-in policy and affording the advantages of store-in cache operation, while simultaneously providing protection against soft-errors in locally modified data, which would normally preclude the use of a store-in cache when reliability is paramount. The improved store-in cache mechanism includes a store-in L1 cache, at least one higher-level storage hierarchy; an ancillary store-only cache (ASOC) that holds most recently stored-to lines of the store-in L1 cache, and a cache controller that controls storing of data to the ancillary store-only cache (ASOC) and recovering of data from the ancillary store-only cache (ASOC) such that the data from the ancillary store-only cache (ASOC) is used only if parity errors are encountered in the store-in L1 cache.

摘要翻译： 提供具有存储策略并提供存储高速缓存操作的优点的缓存系统的系统和方法，同时提供对本地修改的数据中的软错误的保护，这通常会阻止使用存储 缓存当可靠性至关重要时。 改进的存储高速缓存机制包括存储L1高速缓存，至少一个更高级别的存储层级; 保存最近存储在L1高速缓存中的行的辅助存储专用缓存（ASOC）以及控制将数据存储到辅助存储高速缓存（ASOC）并从 辅助存储高速缓存（ASOC），使得只有在存储的L1高速缓存中遇到奇偶校验错误时才使用来自辅助存储高速缓存（ASOC）的数据。

公开(公告)号：US20110026323A1

公开(公告)日：2011-02-03

申请号：US12512582

申请日：2009-07-30

申请人： Wing K. Luk ,  Robert H. Dennard

发明人： Wing K. Luk ,  Robert H. Dennard

IPC分类号： G11C11/36

CPC分类号： G11C11/36 ,  G11C11/404

摘要： A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).

摘要翻译： 提供了门控二极管存储单元，其包括一个或多个晶体管，例如场效应晶体管（“FET”），以及与FET信号通信的门控二极管，使得门控二极管的栅极与源极信号通信 第一FET的栅极，其中栅极二极管的栅极形成存储单元的一个端子，门控二极管的源极形成存储单元的另一个端子，第一FET的漏极与位线（“BL” “），并且第一FET的栅极与写入字线（”WLw“）进行信号通信，并且门控二极管的源极与读取字线（”WLr“）进行信号通信。

公开(公告)号：US07701752B2

公开(公告)日：2010-04-20

申请号：US12266650

申请日：2008-11-07

申请人： Wing K. Luk ,  Brian L. Li

发明人： Wing K. Luk ,  Brian L. Li

IPC分类号： G11C11/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C8/16 ,  G11C11/403 ,  G11C11/405 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2211/4065

摘要： A dynamic random access memory circuit is provided, having at least one write bit line, at least one read bit line, a capacitive storage device, a write access device operatively coupled to the capacitive storage device and the at least one write bit line, a sense amplifier operatively coupled to the at least one read bit line and configured to generate an output signal, a refresh bypass device operatively associated with the sense amplifier and the at least one write bit line so as to selectively pass the output signal to the at least one write bit line, and a write-read bypass device operatively coupled to the at least one write bit line and the at least one read bit line and configured to selectively pass a write signal from a write bit line signal point along the at least one write bit line to a read bit line signal point along the at least one read bit line for output to a data output. the output signal is selectively passed to the at least one write bit line. The write signal is selectively passed from the write bit line signal point along the at least one write bit line to the read bit line signal point along the at least one read bit line for output to the data output.

摘要翻译： 提供了一种动态随机存取存储器电路，其具有至少一个写位线，至少一个读位线，电容存储器件，可操作地耦合到电容存储器件和至少一个写位线的写入存取器件， 感测放大器，其可操作地耦合到所述至少一个读取位线并且被配置为产生输出信号，与所述读出放大器和所述至少一个写入位线可操作地相关联的刷新旁路装置，以选择性地将所述输出信号传递到所述至少一个 一个写入位线以及可操作地耦合到所述至少一个写入位线和所述至少一个读取位线的写入读取旁路器件，并被配置为沿着所述至少一个读取位线选择性地传递来自写入位线信号点的写入信号 将位线沿着至少一个读位线写入读位线信号点，以输出到数据输出。 输出信号被选择性地传递到至少一个写位线。 写入信号从写入位线信号点沿着至少一个写位线选择性地沿着至少一个读位线传递到读位线信号点，以输出到数据输出端。