公开(公告)号：US07927758B2

公开(公告)日：2011-04-19

申请号：US11651830

申请日：2007-01-08

申请人： Dong Uk Lee ,  Jin Hong An ,  Seong Jin An ,  Yeong Chan Eun

发明人： Dong Uk Lee ,  Jin Hong An ,  Seong Jin An ,  Yeong Chan Eun

IPC分类号： H01M2/08 ,  H01M8/10

CPC分类号： H01M8/0273 ,  H01M8/0228 ,  H01M8/0267 ,  H01M8/04552 ,  H01M8/1011 ,  H01M8/242 ,  H01M8/246 ,  Y02E60/523

摘要： A fuel cell system having an electricity generator that generates electricity by the electrochemical reaction between hydrogen and oxygen. The electricity generator includes a membrane electrode assembly with a conductive polymer membrane, and anode and cathode electrode layers on opposite sides of the conductive polymer membrane. The electricity generator has a pair of separator plates facing the anode and cathode electrode layers of the membrane electrode assembly and having channels through which flow hydrogen containing fuel or oxygen containing gas. There is also a pair of gaskets provided on opposite sides of the ionic conductive polymer to enclose each edge of the anode and cathode electrodes so that fluid leakage is prevented between the ionic conductive polymer membrane and the separator plates, wherein at least one of the gaskets is used as a voltage measuring gasket including a nonconductive first frame and a conductive second frame. The voltage measuring gasket having the conductive frame is used for measuring the voltage of the unit cell, thereby preventing a bipolar plate from being damaged.

摘要翻译： 一种燃料电池系统，其具有通过氢和氧之间的电化学反应发电的发电机。 发电机包括具有导电聚合物膜的膜电极组件和在导电聚合物膜的相对侧上的阳极和阴极电极层。 发电机具有面对膜电极组件的阳极和阴极电极层的一对分隔板，并且具有通过其流动含氢燃料或含氧气体的通道。 还存在一对垫片，其设置在离子导电聚合物的相对侧上以包围阳极和阴极电极的每个边缘，使得在离子导电聚合物膜和隔板之间防止流体泄漏，其中至少一个垫圈 被用作包括非导电的第一框架和导电的第二框架的电压测量垫圈。 具有导电框架的电压测量垫圈用于测量单元电池的电压，从而防止双极板被损坏。

公开(公告)号：US06194767B1

公开(公告)日：2001-02-27

申请号：US08495039

申请日：1995-06-27

申请人： Jin Hong An

发明人： Jin Hong An

IPC分类号： H01L2976

CPC分类号： G11C16/0491 ,  G11C17/126 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an X-ROM memory device both metal changeable GND lines and polysilicon changeable GND lines are used as a changeable GND line. The metal changeable GND lines are respectively located on both sides of an array of a fixed number of polysilicon changeable GND lines. Odd polysilicon changeable GND lines are commonly connected to one metal changeable GND line through a predetermined polysilicon line, and even polysilicon changeable GND lines are commonly connected to the other metal changeable GND line through another predetermined polysilicon line. Each of the metal changeable GND lines are then connected to a GND terminal through the driving cell transistors.

摘要翻译： 在X-ROM存储器件中，两个金属可变GND线和多晶硅可变GND线用作可变GND线。 金属可变GND线分别位于固定数量的多晶硅可变GND线的阵列的两侧。 奇数多晶硅可变GND线通常通过预定的多晶硅线连接到一个金属可变GND线，甚至多晶硅可变GND线通常通过另一个预定的多晶硅线连接到另一个金属可变GND线。 然后，每个金属可变GND线通过驱动单元晶体管连接到GND端子。

公开(公告)号：US20100046308A1

公开(公告)日：2010-02-25

申请号：US12609649

申请日：2009-10-30

申请人： Hee Bok KANG ,  Jin Hong An ,  Sung Joo Hong ,  Suk Kyoung Hong

发明人： Hee Bok KANG ,  Jin Hong An ,  Sung Joo Hong ,  Suk Kyoung Hong

IPC分类号： G11C5/14 ,  G11C7/02

CPC分类号： G11C11/404 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4099 ,  G11C2211/4016

摘要： A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages.

摘要翻译： 单晶体管型DRAM包括连接在位线和源极线之间并由字线控制的浮体存储元件。 DRAM包括沿行方向布置的多个源极线和字线，沿列方向布置的多个位线，沿列方向布置的多个参考位线，包括浮体存储元件的单元阵列和 形成在源极线，字线和位线交叉的区域中，形成在源极线，字线和位线交叉配置的区域中的包括浮体存储元件的基准单元阵列 输出具有多个电平的参考电流;多个参考电压产生单元，连接到参考位线并被配置为产生与具有多个电平的参考电流对应的多个参考电压;以及读出放大器和 写入驱动单元连接到位线并被配置为接收多个参考电压。

公开(公告)号：US08189373B2

公开(公告)日：2012-05-29

申请号：US12146583

申请日：2008-06-26

申请人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

IPC分类号： G11C11/00

CPC分类号： G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2211/5634 ,  G11C2213/72 ,  Y10S977/754

摘要： A phase change memory device using a multiple level write voltage is described. The phase change memory device includes a cell array unit including a phase change resistance cell positioned at an intersection of a word line and a bit line. A voltage selection adjusting unit is configured to select one of a plurality of multiple voltages in response to a voltage adjusting signal to output a driving voltage. A write driving unit is also configured to finely adjust the voltage level of the driving voltage in response to a voltage fine-adjusting signal to supply the driving voltage to the cell array unit.

摘要翻译： 描述使用多电平写入电压的相变存储器件。 相变存储器件包括一个单元阵列单元，该单元阵列单元包括位于字线和位线的交点处的相变电阻单元。 电压选择调整单元被配置为响应于电压调整信号选择多个多个电压中的一个以输出驱动电压。 写入驱动单元还被配置为响应于电压微调信号来精细地调节驱动电压的电压电平，以将驱动电压提供给单元阵列单元。

公开(公告)号：US07733718B2

公开(公告)日：2010-06-08

申请号：US12003828

申请日：2008-01-02

申请人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

IPC分类号： G11C7/00

CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10844 ,  H01L29/7841

摘要： A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of clamp bit lines and reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.

摘要翻译： 包括连接在位线和源极线之间并由字线控制的浮体存储元件的单晶体管型DRAM包括排列成行方向的多条源极线和字线， 列方向，沿列方向布置的多个钳位位线和参考位线，包括浮体存储元件并形成在源极线，字线和位线交叉的区域中的单元阵列，钳位 包括浮体存储元件并形成在源极线，字线和位线交叉的区域的单元阵列，包括浮体存储元件的参考单元阵列，并形成在源极线，字线 线和位线交叉，读出放大器和写入驱动单元连接到位线并被配置为接收钳位电压和参考电压。

公开(公告)号：US20090010079A1

公开(公告)日：2009-01-08

申请号：US12003923

申请日：2008-01-03

申请人： Hee Bok Kang ,  Jin Hong An ,  Sung Joo Hong ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Jin Hong An ,  Sung Joo Hong ,  Suk Kyoung Hong

IPC分类号： G11C5/14

CPC分类号： G11C11/404 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4099 ,  G11C2211/4016

摘要： A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages.

公开(公告)号：US20090010052A1

公开(公告)日：2009-01-08

申请号：US12003828

申请日：2008-01-02

申请人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

IPC分类号： G11C11/401

CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10844 ,  H01L29/7841

摘要： A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of clamp bit lines and reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.

摘要翻译： 包括连接在位线和源极线之间并由字线控制的浮体存储元件的单晶体管型DRAM包括排列成行方向的多条源极线和字线， 列方向，沿列方向布置的多个钳位位线和参考位线，包括浮体存储元件并形成在源极线，字线和位线交叉的区域中的单元阵列，钳位 包括浮体存储元件并形成在源极线，字线和位线交叉的区域的单元阵列，包括浮体存储元件的参考单元阵列，并形成在源极线，字线 线和位线交叉，读出放大器和写入驱动单元连接到位线并被配置为接收钳位电压和参考电压。

公开(公告)号：US08416638B2

公开(公告)日：2013-04-09

申请号：US12164216

申请日：2008-06-30

申请人： Dong Hwee Kim ,  Jin Hong An

发明人： Dong Hwee Kim ,  Jin Hong An

IPC分类号： G11C8/08

CPC分类号： G11C8/08 ,  G11C8/14

摘要： A semiconductor memory device includes a main word line shared by a plurality of mats. Each of the mats includes a plurality of sub word lines. A decoding unit is configured to decode a row address bit and output a word line driving signal. A plurality of sub word line driving units are each configured to activate one of the sub word lines according to the word line driving signal. In the semiconductor memory device each neighboring sub word line driving units is connected to a different main word line to remove parasitic coupling capacitance.

摘要翻译： 半导体存储器件包括由多个垫共享的主字线。 每个垫包括多个子字线。 解码单元被配置为对行地址位进行解码并输出字线驱动信号。 多个子字线驱动单元被配置为根据字线驱动信号激活子字线中的一个。 在半导体存储器件中，每个相邻的子字线驱动单元连接到不同的主字线以去除寄生耦合电容。

公开(公告)号：US07668031B2

公开(公告)日：2010-02-23

申请号：US11967531

申请日：2007-12-31

申请人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

IPC分类号： G11C7/02

CPC分类号： G11C7/14 ,  G11C11/22

摘要： A semiconductor memory device includes a one-transistor (1-T) field effect transistor (FET) type memory cell connected between a pair of bit lines, and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer. The device includes a plurality of word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a pair of clamp dummy lines arranged in the column direction, a pair of reference dummy lines arranged in the column direction, a cell array including the memory cell and formed in a region where the word line and the bit line are crossed, a dummy cell array including the memory cell and formed where the word line, the pair of claim dummy lines and the pair of reference dummy lines are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.

摘要翻译： 半导体存储器件包括连接在一对位线之间并由字线控制的单晶体管（1-T）场效应晶体管（FET）型存储单元，其中不同的沟道电阻被引导到通道区域依赖 在铁电层的极性状态。 该装置包括排列成行方向的多个字线，沿列方向配置的多个位线，沿列方向排列的一对钳位虚拟线，沿列方向排列的一对基准虚拟线， 包括存储单元并形成在字线和位线交叉的区域中的单元阵列，包括存储单元的虚拟单元阵列，并形成在字线，一对声线虚拟线和一对参考虚线之间 以及连接到位线并被配置为接收钳位电压和参考电压的读出放大器和写入驱动单元。

公开(公告)号：US07663910B2

公开(公告)日：2010-02-16

申请号：US12135241

申请日：2008-06-09

申请人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

IPC分类号： G11C11/00

CPC分类号： G11C13/0038 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

摘要： A phase change memory device includes a plurality of word lines arranged in a row direction and a plurality of bit lines arranged in a column direction. A plurality of reference bit line and a plurality of clamp bit lines are arranged in the column direction. A cell array block including a phase change resistance cell is arranged where a word line and a bit line intersect. A reference cell array block is formed where a word line and the reference bit line intersect. The reference cell array block is configured to output a reference current. A clamp cell array block is formed where a word line and a clamp bit line intersect. The clamp cell array block is configured to output a clamp current. A sense amplifier is connected to each of the bit lines and is configured to receive a clamp voltage and a reference voltage.

摘要翻译： 相变存储器件包括沿行方向布置的多个字线和沿列方向布置的多个位线。 多个基准位线和多个钳位位线在列方向上排列。 布置包括相变电阻单元的单元阵列块，其中字线和位线相交。 形成参考单元阵列块，其中字线和参考位线相交。 参考单元阵列块被配置为输出参考电流。 形成钳位单元阵列块，其中字线和钳位位线相交。 钳位单元阵列块被配置为输出钳位电流。 感测放大器连接到每个位线，并且被配置为接收钳位电压和参考电压。