公开(公告)号：US10608641B2

公开(公告)日：2020-03-31

申请号：US16041602

申请日：2018-07-20

Applicant: Xilinx, Inc.

Inventor： Hao Yu ,  Raymond Kong ,  Brian S. Martin ,  Jun Liu

IPC: G06F17/50 ,  G06F15/78 ,  H03K19/17756 ,  H03K19/1776 ,  H03K19/17736 ,  H03K19/17728 ,  H03K19/177

Abstract: Hierarchical partial reconfiguration for integrated circuits includes converting, using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading, using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including, using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.

公开(公告)号：US11449347B1

公开(公告)日：2022-09-20

申请号：US16421367

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Raymond Kong ,  Brian S. Martin ,  Hao Yu ,  Jun Liu ,  Ashish Sirasao

IPC: G06F9/445 ,  G06F16/22 ,  G06F9/48 ,  G06F16/28 ,  G06F9/50 ,  G06F30/34

Abstract: Time-multiplexing implementation of hardware accelerated functions includes associating each function of a plurality of functions from program code with an accelerator binary image specifying a hardware accelerated version of the associated function and determining which accelerator binary images are data independent. Using the computer hardware, the accelerator binary images can be scheduled for implementation in a programmable integrated circuit within each of a plurality of partial reconfiguration regions based on data independence.

公开(公告)号：US10963613B1

公开(公告)日：2021-03-30

申请号：US16523973

申请日：2019-07-26

Applicant: Xilinx, Inc.

Inventor： Meiwei Wu ,  Jun Liu ,  Raymond Kong

IPC: G06F17/50 ,  G06F30/34 ,  G06F30/392

Abstract: Partial reconfiguration of a programmable integrated circuit can include loading, using computer hardware, a platform design including a module black-box instance corresponding to a user design and marking, using the computer hardware, data of the platform design including data relating to synchronous boundary crossings between the platform design and the module black-box instance and implementation data for the platform design within an extended routing region available for routing the user design. Unmarked data can be removed from the platform design resulting in a shell circuit design. The user design can be implemented based on the shell circuit design and timing constraints corresponding to the marked data in the shell circuit design.

公开(公告)号：US10893005B2

公开(公告)日：2021-01-12

申请号：US16133357

申请日：2018-09-17

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Ian A. Swarbrick ,  Jun Liu ,  Raymond Kong ,  Herve Alexanian

IPC: H04L12/931 ,  G06F15/78 ,  H04L12/933 ,  H04L12/761

Abstract: Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.

公开(公告)号：US20230148419A1

公开(公告)日：2023-05-11

申请号：US17522834

申请日：2021-11-09

Applicant: Xilinx, Inc.

Inventor： Hao Yu ,  Jun Liu

IPC: G06F30/343 ,  G06F30/347 ,  G06F30/327

CPC classification number: G06F30/343 ,  G06F30/347 ,  G06F30/327

Abstract: Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s) corresponding to the additional port(s) can be created. The circuit design, including the current RM instance, the additional port(s), and the net(s), can be placed and routed. Prior to the inserting and the performing place and route for a next RM instance to be inserted into the RM, the current RM instance can be removed from the RM along with the additional port(s) and the net(s).