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公开(公告)号：US10371725B1
公开(公告)日：2019-08-06
申请号：US15994060
申请日：2018-05-31
Applicant: Xilinx, Inc.
Inventor： Alonso Morgado , Bruno Miguel Vaz , Edward Cullen , Christophe Erdmann
IPC: G08B21/00 , G01R19/165 , H02H9/04 , H03K19/003
Abstract: Examples of the present disclosure provide out-of-range voltage detection and protection in integrated circuits (ICs). In some examples, an IC includes an envelope detector, a comparator, and a switch. The envelope detector is configured to generate an envelope signal of a signal and output the envelope signal on an output node of the envelope detector. A first input node of the comparator is coupled to the output node of the envelope detector. The comparator is configured to compare respective signals provided on the first and second input nodes of the comparator and generate a comparison signal in response to the comparison. The comparator is further configured to output the comparison signal on the output node of the comparator. The switch is connected between a protected node and a protection node and is configured to be selectively opened or closed based, at least in part, on the comparison signal.
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12.发明授权公开(公告)号：US10290330B1
公开(公告)日：2019-05-14
申请号：US15832515
申请日：2017-12-05
Applicant: Xilinx, Inc.
Inventor： Umanath R. Kamath , John K. Jennings , Edward Cullen , Ionut C. Cical , Darragh Walsh
Abstract: An example voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the complementary-to-temperature current.
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公开(公告)号：US09377795B1
公开(公告)日：2016-06-28
申请号：US14543526
申请日：2014-11-17
Applicant: Xilinx, Inc.
Inventor： Ionut C. Cical , Edward Cullen
CPC classification number: G05F1/463 , G05F1/468 , H03F1/30 , H03F2200/447
Abstract: In an example, a temperature-corrected voltage reference circuit for use in an integrated circuit (IC) includes a voltage reference circuit, a programmable gain amplifier, and a digital control circuit. The programmable gain amplifier includes a first input coupled to the voltage reference circuit, a second input coupled to receive a control signal, and an output coupled to provide a temperature-corrected voltage reference. The digital control circuit includes an input coupled to receive a temperature signal indicative of temperature of the IC and an output coupled to the second input of the programmable gain amplifier, the digital control circuit generating the control signal in response to the temperature signal.
Abstract translation: 在一个示例中，用于集成电路（IC）的温度校正的电压参考电路包括电压参考电路，可编程增益放大器和数字控制电路。 可编程增益放大器包括耦合到电压参考电路的第一输入，耦合以接收控制信号的第二输入，以及耦合以提供温度校正的电压基准的输出。 数字控制电路包括耦合以接收指示IC的温度的温度信号和耦合到可编程增益放大器的第二输入的输出的输入，数字控制电路响应于温度信号产生控制信号。
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14.发明授权公开(公告)号：US09312586B2
公开(公告)日：2016-04-12
申请号：US13675780
申请日：2012-11-13
Applicant: Xilinx, Inc.
Inventor： Donnacha Lowney , Edward Cullen
CPC classification number: H01P1/20 , G11C27/024 , H03H7/0123 , H03H7/38 , H03H2007/013 , H04B3/20
Abstract: A circuit includes a first input terminal, a first transmission line, a first sampling switch coupled to the first input terminal through the first transmission line, a first sampling capacitor coupled to the sampling switch, and a first open-circuit quarter wavelength stub coupled to the first transmission line, the first open-circuit quarter wavelength stub configured to reduce kickback noise on the first transmission line. A method for reducing kickback noise in a circuit includes determining a frequency associated with a kickback noise on a first transmission line of the circuit, the circuit having an input terminal coupled to the first transmission line, configuring a length of an open-circuit quarter wavelength stub to correspond to the determined frequency, and coupling the open-circuit quarter wavelength stub to the first transmission line to filter the frequency associated with the kickback noise.
Abstract translation: 电路包括第一输入端，第一传输线，通过第一传输线耦合到第一输入端的第一采样开关，耦合到采样开关的第一采样电容器和耦合到第一开路四分之一波长短截线 所述第一传输线，所述第一开路四分之一波长短截线被配置为减少所述第一传输线上的反冲噪声。 一种用于减少电路中的反冲噪声的方法包括确定与电路的第一传输线上的反冲噪声相关的频率，该电路具有耦合到第一传输线的输入端，配置开路四分之一波长的长度 短截线对应于所确定的频率，并且将开路四分之一波长短截线耦合到第一传输线以滤除与反冲噪声相关联的频率。
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公开(公告)号：US20140266824A1
公开(公告)日：2014-09-18
申请号：US13843909
申请日：2013-03-15
Applicant: XILINX, INC.
Inventor： Donnacha Lowney , Christophe Erdmann , Edward Cullen
IPC: H03M1/10
CPC classification number: H03M1/1009 , H03M1/742
Abstract: An apparatus for calibration of a signal converter is disclosed. This apparatus includes a first digital-to-analog converter (“DAC”) and a calibration system coupled to an output port of the first DAC. The calibration system includes a second DAC. The calibration system is configured to provide an adjustment signal responsive to a spurious spectral performance parameter in an output of the first DAC. The spurious spectral performance parameter is sensitive to a timing error associated with the first DAC. The calibration system is coupled to provide the adjustment signal to the first DAC to correct the timing error of the first DAC.
Abstract translation: 公开了一种用于校准信号转换器的装置。 该装置包括第一数模转换器（“DAC”）和耦合到第一DAC的输出端口的校准系统。 校准系统包括第二DAC。 校准系统被配置为响应于第一DAC的输出中的寄生光谱性能参数提供调整信号。 寄生光谱性能参数对与第一个DAC相关的定时误差敏感。 校准系统被耦合以向第一DAC提供调整信号以校正第一DAC的定时误差。
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Patent Agency Ranking
公开(公告)号：US08836409B1
公开(公告)日：2014-09-16
申请号：US13792949
申请日：2013-03-11
Applicant: Xilinx, Inc.
Inventor： Edward Cullen , April M. Graham , Ionut C. Cical
IPC: H03K17/687
CPC classification number: H03K17/08122 , H03K17/06 , H03K2017/066 , H03K2217/0054
Abstract: An apparatus includes: a switch having a first transistor, the first transistor having a gate, wherein the switch is connected between a first pad and a second pad; and a first biasing circuit coupled to the gate of the first transistor, wherein the first biasing circuit is configured for outputting a first voltage, the first voltage being the lowest one of (1) a voltage of the first pad, (2) a voltage of the second pad, and (3) a ground voltage; wherein the gate of the first transistor is driven by the first voltage from the first biasing circuit in response to an enable signal being set for configuring the switch to be off.
Abstract translation: 一种装置包括：具有第一晶体管的开关，所述第一晶体管具有栅极，其中所述开关连接在第一焊盘和第二焊盘之间; 以及耦合到所述第一晶体管的栅极的第一偏置电路，其中所述第一偏置电路被配置为输出第一电压，所述第一电压是（1）第一焊盘的电压中的最低电压，（2） 的第二焊盘，（3）接地电压; 其中响应于将所述开关配置为断开而设置的使能信号，来自所述第一偏置电路的所述第一晶体管的栅极被所述第一电压驱动。
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公开(公告)号：US11604490B1
公开(公告)日：2023-03-14
申请号：US17500711
申请日：2021-10-13
Applicant: XILINX, INC.
Inventor： Roswald Francis , Edward Cullen
Abstract: Techniques and apparatus for reducing low frequency power supply spurs in clock signals. One example circuit generally includes a first power supply circuit configured to generate a first power supply voltage on a first power supply rail, a second power supply circuit configured to generate a second power supply voltage on a second power supply rail, a clock distribution network, and a feedback circuit coupled between the second power supply rail and at least one input of the first power supply circuit. The feedback circuit may be configured to sense the second power supply voltage, to process the sensed second power supply voltage, and to output at least one feedback signal to control the first power supply circuit based on the processed second power supply voltage. The clock distribution network may include first and second sets of clock drivers powered by the first and second power supply voltages, respectively.
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公开(公告)号：US11003204B1
公开(公告)日：2021-05-11
申请号：US16216990
申请日：2018-12-11
Applicant: Xilinx, Inc.
Inventor： Ionut C. Cical , Edward Cullen , Brendan Farley
IPC: G06F1/08 , G06F1/324 , H03K3/0231 , H03K3/011 , G06F1/3296 , H03B5/12 , H03L7/099
Abstract: Examples described herein provide for a relaxation oscillator and corresponding methods of operation. In an example, a circuit includes a dynamically controllable current source, a capacitor, and an oscillator generation circuit. The dynamically controllable current source includes a digitally tunable current mirror configured to generate a current. The digitally tunable current mirror includes multiple transistors configured to be selectively electrically connected in parallel to alter a gain of the digitally tunable current mirror to control the current. The capacitor is selectively electrically connected to the dynamically controllable current source. The oscillator generation circuit is electrically connected to the capacitor. The oscillator generation circuit is configured to generate an oscillation signal in response to a voltage of the capacitor.
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19.发明授权公开(公告)号：US10680583B1
公开(公告)日：2020-06-09
申请号：US16286489
申请日：2019-02-26
Applicant: Xilinx, Inc.
Inventor： Umanath R. Kamath , Diarmuid Collins , Edward Cullen
Abstract: A control circuit used in an integrated circuit device is described. The control circuit comprises a startup timer configured to generate a startup timing signal; a startup circuit configured to generate a startup control signal; and a switching element coupled between the startup circuit and a load; wherein the switching element applies the startup control signal to the load during a startup period associated with the startup timing signal. A method of controlling an operation of an integrated circuit device is also described.
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20.发明申请公开(公告)号：US20190172504A1
公开(公告)日：2019-06-06
申请号：US15832515
申请日：2017-12-05
Applicant: Xilinx, Inc.
Inventor： Umanath R. Kamath , John K. Jennings , Edward Cullen , Ionut C. Cical , Darragh Walsh
Abstract: An example voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the complementary-to-temperature current.
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