公开(公告)号：US11302674B2

公开(公告)日：2022-04-12

申请号：US16880811

申请日：2020-05-21

Applicant: XILINX, INC.

Inventor： Jaspreet Singh Gandhi ,  Suresh Ramalingam ,  William E. Allaire ,  Hong Shi ,  Kerry M. Pierce

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.

公开(公告)号：US20180338375A1

公开(公告)日：2018-11-22

申请号：US15597505

申请日：2017-05-17

Applicant: Xilinx, Inc.

Inventor： Hong Shi ,  Siow Chek Tan

IPC: H05K1/02 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H05K1/14 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/0228 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H05K1/111 ,  H05K1/115 ,  H05K1/144 ,  H05K1/181 ,  H01L2924/014

Abstract: An integrated circuit device having a vertical connection interfaces for coupling stacked components are provided that improve communication between the stacked components. The techniques described herein allow for increased signal connection density while reducing potential for crosstalk. For example, a ground to signal ratio of connections between components in a vertical interface configured to carry ground signals relative to connections configured to carry data signals within a bank of connections has an edge to center gradient which reduces the amount of ground connections needed to meet crosstalk thresholds, while increasing the amount of signal connections available for communication between components across the vertical interface.