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    Chip scale package (CSP) including shim die
    1.
    发明授权
    Chip scale package (CSP) including shim die 有权

    公开(公告)号：US10770364B2

    公开(公告)日：2020-09-08

    申请号：US15951941

    申请日：2018-04-12

    Applicant: Xilinx, Inc.

    Inventor： Hong Shi ,  Suresh Ramalingam ,  Siow Chek Tan ,  Gamal Refai-Ahmed

    IPC: H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065

    Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.

    Low crosstalk vertical connection interface
    2.
    发明授权
    Low crosstalk vertical connection interface 有权

    公开(公告)号：US10314163B2

    公开(公告)日：2019-06-04

    申请号：US15597505

    申请日：2017-05-17

    Applicant: Xilinx, Inc.

    Inventor： Hong Shi ,  Siow Chek Tan

    IPC: H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065

    Abstract: An integrated circuit device having a vertical connection interfaces for coupling stacked components are provided that improve communication between the stacked components. The techniques described herein allow for increased signal connection density while reducing potential for crosstalk. For example, a ground to signal ratio of connections between components in a vertical interface configured to carry ground signals relative to connections configured to carry data signals within a bank of connections has an edge to center gradient which reduces the amount of ground connections needed to meet crosstalk thresholds, while increasing the amount of signal connections available for communication between components across the vertical interface.

    Method and apparatus of package enabled ESD protection
    4.
    发明授权
    Method and apparatus of package enabled ESD protection 有权

    公开(公告)号：US11043484B1

    公开(公告)日：2021-06-22

    申请号：US16362134

    申请日：2019-03-22

    Applicant: Xilinx, Inc.

    Inventor： Hong Shi ,  James Karp ,  Siow Chek Tan ,  Martin L. Voogel ,  Mohsen H. Mardi ,  Suresh Ramalingam ,  David M. Mahoney

    IPC: H01L27/02 ,  G01R1/04 ,  H01L25/065 ,  H01L23/498

    Abstract: Techniques for electrostatic discharge (ESD) protection in integrated circuit (IC) chip packages methods for testing the same are described that are configured to directs the risk of ESD events through ground and power interconnects preferentially over I/O interconnects to enhance ESD protection in chip packages. In one example, a chip package is provided that includes an IC die, a substrate, and a plurality of interconnects. The plurality of interconnects are exposed on a side of the substrate opposite the IC die. The interconnects provide terminations for substrate circuitry formed within the substrate. At least one of the last 5 interconnects of the plurality of interconnects respectively comprising rows and columns of interconnects disposed along the edges of the substrate that closest to each corner of substrate project farther from the substrate than interconnects within those rows and columns that are configured as I/O interconnects.

    CHIP SCALE PACKAGE (CSP) INCLUDING SHIM DIE
    5.
    发明申请
    CHIP SCALE PACKAGE (CSP) INCLUDING SHIM DIE 审中-公开

    公开(公告)号：US20190318975A1

    公开(公告)日：2019-10-17

    申请号：US15951941

    申请日：2018-04-12

    Applicant: Xilinx, Inc.

    Inventor： Hong Shi ,  Suresh Ramalingam ,  Siow Chek Tan ,  Gamal Refai-Ahmed

    IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367

    Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.

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