公开(公告)号：US12136613B2

公开(公告)日：2024-11-05

申请号：US17669252

申请日：2022-02-10

Applicant: XILINX, INC.

Inventor： Li-Sheng Weng ,  Suresh Ramalingam ,  Hong Shi

IPC: H01L23/00 ,  H01L25/16

Abstract: A chip package and method for fabricating the same are provided that includes a near-die integrated passive device. The near-die integrated passive device is disposed between a package substrate and an integrated circuit die of a chip package. Some non-exhaustive examples of an integrated passive device that may be disposed between the package substrate and the integrated circuit die include a resistor, a capacitor, an inductor, a coil, a balum, or an impedance matching element, among others.

公开(公告)号：US10770364B2

公开(公告)日：2020-09-08

申请号：US15951941

申请日：2018-04-12

Applicant: Xilinx, Inc.

Inventor： Hong Shi ,  Suresh Ramalingam ,  Siow Chek Tan ,  Gamal Refai-Ahmed

IPC: H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065

Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.

公开(公告)号：US10314163B2

公开(公告)日：2019-06-04

申请号：US15597505

申请日：2017-05-17

Applicant: Xilinx, Inc.

Inventor： Hong Shi ,  Siow Chek Tan

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065

Abstract: An integrated circuit device having a vertical connection interfaces for coupling stacked components are provided that improve communication between the stacked components. The techniques described herein allow for increased signal connection density while reducing potential for crosstalk. For example, a ground to signal ratio of connections between components in a vertical interface configured to carry ground signals relative to connections configured to carry data signals within a bank of connections has an edge to center gradient which reduces the amount of ground connections needed to meet crosstalk thresholds, while increasing the amount of signal connections available for communication between components across the vertical interface.

公开(公告)号：US20150282299A1

公开(公告)日：2015-10-01

申请号：US14242795

申请日：2014-04-01

Applicant: XILINX, INC.

Inventor： Hong Shi ,  Paul Y. Wu ,  Jian Tu

IPC: H05K1/02

CPC classification number: H01L23/66 ,  H01L23/49827 ,  H01L24/16 ,  H01L2223/6627 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19107

Abstract: Embodiments of the invention generally provide an electronic device comprising an electrical interconnect component that includes an electrical trace. The electrical trace has geometric characteristics that serve to suppress the skin effect over a large band of frequency components. More specifically, the electrical trace has a thickness that is less than a skin depth for a particular chosen frequency component. By making the electrical trace have a thickness that is less than the skin depth, the current flows through substantially the entire cross-sectional area of the electrical trace for all frequencies up to the chosen frequency component, which reduces the effects associated with the skin effect.

Abstract translation: 本发明的实施例通常提供一种包括电互连部件的电子设备，其包括电迹线。 电迹线具有几何特征，其用于抑制大频带组件的皮肤效应。 更具体地，电迹线具有小于特定选定频率分量的趋肤深度的厚度。 通过使电迹线具有小于皮肤深度的厚度，电流流过所有频率的电迹线的整个横截面积直到选定的频率分量，这降低了与皮肤效应相关的影响 。

公开(公告)号：US11688675B1

公开(公告)日：2023-06-27

申请号：US17315229

申请日：2021-05-07

Applicant: XILINX, INC.

Inventor： Frank Peter Lambrecht ,  Po-Wei Chiu ,  Hong Shi

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/552

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/552

Abstract: Various noise isolation structures and methods for fabricating the same are presented. In one example, a substrate for chip package is provided. The substrate includes a core region, top build-up layers and bottom build-up layers. The top build-up layers are formed on a first side of the core region and the bottom build-up layers are formed on a second side of the core region that is opposite the first side. Routing circuitry formed in the bottom build-up layers is coupled to routing circuitry formed in the top build-up layers by vias formed through the core region. A void is formed in the bottom build-up layers. The void is configured as a noise isolation structure. The void has a sectional area that is different in at least two different distances from the core region.

公开(公告)号：US11950358B1

公开(公告)日：2024-04-02

申请号：US17357089

申请日：2021-06-24

Applicant: XILINX, INC.

Inventor： Frank Peter Lambrecht ,  Brian D. Philofsky ,  Hong Shi ,  Prasun Raha

IPC: H05K1/02

CPC classification number: H05K1/0262

Abstract: A semiconductor device system comprises an integrated circuit (IC) die. The IC die is configured to operate in a first operating mode during a first period, and a second operating mode during a second period. The first period is associated with enabling an element of the IC die and a first amount of voltage droop. The second period occurs after the first period and is associated with a second amount of voltage droop. The second amount of voltage droop is less than the first amount of voltage droop.

公开(公告)号：US11043484B1

公开(公告)日：2021-06-22

申请号：US16362134

申请日：2019-03-22

Applicant: Xilinx, Inc.

Inventor： Hong Shi ,  James Karp ,  Siow Chek Tan ,  Martin L. Voogel ,  Mohsen H. Mardi ,  Suresh Ramalingam ,  David M. Mahoney

IPC: H01L27/02 ,  G01R1/04 ,  H01L25/065 ,  H01L23/498

Abstract: Techniques for electrostatic discharge (ESD) protection in integrated circuit (IC) chip packages methods for testing the same are described that are configured to directs the risk of ESD events through ground and power interconnects preferentially over I/O interconnects to enhance ESD protection in chip packages. In one example, a chip package is provided that includes an IC die, a substrate, and a plurality of interconnects. The plurality of interconnects are exposed on a side of the substrate opposite the IC die. The interconnects provide terminations for substrate circuitry formed within the substrate. At least one of the last 5 interconnects of the plurality of interconnects respectively comprising rows and columns of interconnects disposed along the edges of the substrate that closest to each corner of substrate project farther from the substrate than interconnects within those rows and columns that are configured as I/O interconnects.

公开(公告)号：US20190318975A1

公开(公告)日：2019-10-17

申请号：US15951941

申请日：2018-04-12

Applicant: Xilinx, Inc.

Inventor： Hong Shi ,  Suresh Ramalingam ,  Siow Chek Tan ,  Gamal Refai-Ahmed

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367

Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.

公开(公告)号：US10057976B1

公开(公告)日：2018-08-21

申请号：US15692975

申请日：2017-08-31

Applicant: Xilinx, Inc.

Inventor： Hong Shi ,  Siow Chek Tan ,  Sarajuddin Niazi

IPC: H01L23/49 ,  H01L23/64 ,  H01L23/66 ,  H05K1/02 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/552 ,  H03H7/01 ,  H01L25/065 ,  H05K1/18 ,  H01L23/538

CPC classification number: H05K1/0231 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/538 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H01L23/642 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/3025 ,  H03H7/0115 ,  H05K1/0216 ,  H05K1/0233 ,  H05K1/162 ,  H05K1/181 ,  H05K2201/10734 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An interface layout for a vertical interface of a first semiconductor component is disclosed. A first one or more conductors configured to carry power signals extends vertically from the first semiconductor component. A second one or more conductors configured to carry data signals extends vertically from the first semiconductor component. A third one or more conductors configured to carry ground signals extending vertically from the first semiconductor component. The first one or more conductors are further configured to shield and separate the second one or more conductors. A fourth one or more conductors extends horizontally from the first one or more conductors adjacent to and terminating proximal to the third one or more conductors. A fifth one or more conductors extending horizontally from the third one or more conductors adjacent to and terminating proximal to the first one or more conductors and the fourth one or more conductors. The fourth one or more conductors and the corresponding adjacent fifth one or more conductors form a plate capacitor.

公开(公告)号：US11735519B2

公开(公告)日：2023-08-22

申请号：US17357087

申请日：2021-06-24

Applicant: XILINX, INC.

Inventor： Zhaoyin Daniel Wu ,  Parag Upadhyaya ,  Hong Shi

IPC: H01L23/522 ,  H01Q1/22

CPC classification number: H01L23/5227 ,  H01Q1/2283 ,  H01L2223/6672 ,  H01L2223/6677

Abstract: A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.