公开(公告)号：US08775986B1

公开(公告)日：2014-07-08

申请号：US13776350

申请日：2013-02-25

Applicant: Xilinx, Inc.

Inventor： Sundararajarao Mohan ,  L. James Hwang

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F11/3624 ,  G06F2217/14

Abstract: A method is provided for synthesizing an HLL program. For one or more variables to observe and/or control in a function of the HLL program, a first code segment is added to the function in the HLL program. For each of the one or more variables a respective second code segment is also added to the HLL program. In response to encountering the first code segment during synthesis of the HLL program, a memory is instantiated in a synthesized design. In response to encountering the second code segment during synthesis of the HLL program, a respective interface circuit is instantiated in the synthesized design. Each interface circuit is configured to replicate a state of the corresponding variable in the memory during operation of the synthesized design. A table is generated that maps names of the one or more variables to respective memory addresses in the memory.

Abstract translation: 提供了一种用于合成HLL程序的方法。 对于一个或多个变量来观察和/或控制HLL程序的功能，第一代码段被添加到HLL程序中的功能。 对于一个或多个变量中的每一个，相应的第二代码段也被添加到HLL程序。 响应在HLL程序的合成期间遇到第一代码段，在合成设计中实例化存储器。 响应于在HLL程序的合成期间遇到第二代码段，在合成设计中实例化了相应的接口电路。 每个接口电路被配置为在合成设计的操作期间复制存储器中相应变量的状态。 生成一个表，将一个或多个变量的名称映射到存储器中的各个存储器地址。

公开(公告)号：US20230367923A1

公开(公告)日：2023-11-16

申请号：US17662818

申请日：2022-05-10

Applicant: Xilinx, Inc.

Inventor： Ji Yang ,  Haris Javaid ,  Sundararajarao Mohan

IPC: G06F30/20 ,  H04L9/00

CPC classification number: G06F30/20 ,  H04L9/50 ,  G06F2111/02

Abstract: A simulation framework is capable modeling a hardware implementation of a reference software system using models specified in different computer-readable languages. The models correspond to different ones of a plurality of subsystems of the hardware implementation. Input data is provided to a first simulator configured to simulate a first model of a first subsystem of the modeled hardware implementation. The input data is captured from execution of the reference software system. The first simulator executing the first model generates a first data file specifying output of the first subsystem. The first data file specifies intermediate data of the modeled hardware implementation. The first data file is provided to a second simulator configured to simulate a second model of a second subsystem of the modeled hardware implementation. The second simulator executing the second model generates a second data file specifying output of the second subsystem.

公开(公告)号：US10573598B2

公开(公告)日：2020-02-25

申请号：US15719288

申请日：2017-09-28

Applicant: Xilinx, Inc.

Inventor： Austin H. Lesea ,  Sundararajarao Mohan ,  Stephen M. Trimberger

IPC: G06F15/78 ,  H01L23/538 ,  H01L23/50

Abstract: An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.

公开(公告)号：US09880966B1

公开(公告)日：2018-01-30

申请号：US14845127

申请日：2015-09-03

Applicant: Xilinx, Inc.

Inventor： L. James Hwang ,  Vinod K. Kathail ,  Sundararajarao Mohan ,  Jorge E. Carrillo ,  Hua Sun

IPC: G06F13/24 ,  G06F13/40 ,  G06F13/42 ,  G06F3/00

CPC classification number: G06F13/4256 ,  G06F13/24 ,  G06F13/4022

Abstract: Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.

公开(公告)号：US09223921B1

公开(公告)日：2015-12-29

申请号：US14540854

申请日：2014-11-13

Applicant: Xilinx, Inc.

Inventor： Jorge E. Carrillo ,  L. James Hwang ,  Hua Sun ,  Sundararajarao Mohan ,  Vinod K. Kathail

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F8/447

Abstract: In an example implementation, a method is provided for compiling an HLL source file. The HLL source file checked for function calls to a set of hardware-accelerated functions having hardware implementations specified in a hardware library. For each HLL function call to a hardware-accelerated function, a circuit design is retrieved from the hardware library. The circuit design specifies a hardware implementation of the hardware-accelerated function. HLL interface code configured to communicate with the hardware implementation of the hardware-accelerated function is also generated. The HLL function call to the hardware-accelerated function in the HLL source file is replaced with the generated interface code. The HLL source file is compiled to generate a program executable on a processor of a programmable IC. Configuration data is generated that implements the retrieved circuit designs on the programmable circuitry of the programmable IC.

Abstract translation: 在一个示例实现中，提供了一种用于编译HLL源文件的方法。 HLL源文件检查了对硬件库中指定的硬件实现的一组硬件加速功能的函数调用。 对于硬件加速功能的每个HLL函数调用，从硬件库检索电路设计。 电路设计规定了硬件加速功能的硬件实现。 HLL接口代码配置为与硬件通信实现硬件加速功能也被生成。 HLL源文件中的硬件加速功能的HLL函数调用将替换为生成的接口代码。 HLL源文件被编译成在可编程IC的处理器上生成可执行的程序。 生成配置数据，其实现在可编程IC的可编程电路上检索的电路设计。

公开(公告)号：US08762916B1

公开(公告)日：2014-06-24

申请号：US13776318

申请日：2013-02-25

Applicant: Xilinx, Inc.

Inventor： Vinod K. Kathail ,  L. James Hwang ,  Sundararajarao Mohan ,  Hua Sun

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5054

Abstract: A method of automatically developing a data transfer network includes determining, using a processor, a plurality of data transfers of a function of a circuit design marked for hardware acceleration within a target integrated circuit. The circuit design is specified in a high level programming language, and at least one other function of the circuit design remains executable by a microprocessor of the target integrated circuit. Each of the plurality of data transfers is characterized. Each of the plurality of data transfers is correlated with resources of the target integrated circuit. A programmatic description of a data transfer network is generated for the circuit design. The data transfer network connects the hardware accelerator and the microprocessor according to the characterizing and the correlating.

Abstract translation: 自动开发数据传输网络的方法包括：使用处理器来确定在目标集成电路内标记为硬件加速的电路设计的功能的多个数据传输。 电路设计以高级编程语言指定，并且电路设计的至少一个其他功能仍然可以由目标集成电路的微处理器执行。 多个数据传输中的每一个都被表征。 多个数据传输中的每一个与目标集成电路的资源相关。 为电路设计生成数据传输网络的编程描述。 数据传输网络根据特征和相关性连接硬件加速器和微处理器。