公开(公告)号：US07869273B2

公开(公告)日：2011-01-11

申请号：US11849992

申请日：2007-09-04

申请人： Dana Lee ,  Emilio Yero

发明人： Dana Lee ,  Emilio Yero

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

摘要翻译： 提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。 存储单元分为两个或更多个组。 在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。 在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。 在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。 在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。 在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

公开(公告)号：US07451264B2

公开(公告)日：2008-11-11

申请号：US11404672

申请日：2006-04-13

申请人： Emilio Yero

发明人： Emilio Yero

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A hot count records the number of erase operations experienced by a block. The hot count is stored in an overhead data area of the block and is updated by circuits located on the same substrate as the block. Where a memory has two or more planes, each plane has circuits for updating hot counts.

摘要翻译： 热计数记录块所经历的擦除操作的数量。 热计数存储在块的开销数据区域中，并且通过位于与块相同的衬底上的电路来更新。 在存储器具有两个或更多个平面的情况下，每个平面具有用于更新热计数的电路。

公开(公告)号：US20070245068A1

公开(公告)日：2007-10-18

申请号：US11404672

申请日：2006-04-13

申请人： Emilio Yero

发明人： Emilio Yero

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A hot count records the number of erase operations experienced by a block. The hot count is stored in an overhead data area of the block and is updated by circuits located on the same substrate as the block. Where a memory has two or more planes, each plane has circuits for updating hot counts.

摘要翻译： 热计数记录块所经历的擦除操作的数量。 热计数存储在块的开销数据区域中，并且通过位于与块相同的衬底上的电路来更新。 在存储器具有两个或更多个平面的情况下，每个平面具有用于更新热计数的电路。

公开(公告)号：US06140876A

公开(公告)日：2000-10-31

申请号：US188071

申请日：1998-11-06

申请人： Emilio Yero

发明人： Emilio Yero

IPC分类号： H03F3/45

CPC分类号： H03F3/4565 ,  H03F3/45183 ,  H03F3/45659 ,  H03F2203/45112 ,  H03F2203/45648

摘要： In a differential amplifier with asymmetrical outputs, the gates of the two load transistors are at the same specified potential and the voltage at the connection node between the load transistor and the amplifier transistor of one arm is stabilized by means of a compensation structure. This amplifier works at low VCC (e.g., less than 2 volts) while at the same time having high gain.

摘要翻译： 在具有不对称输出的差分放大器中，两个负载晶体管的栅极处于相同的指定电位，负载晶体管和一个臂的放大器晶体管之间的连接节点处的电压通过补偿结构来稳定。 该放大器工作在低VCC（例如，小于2伏特），同时具有高增益。

公开(公告)号：US5923590A

公开(公告)日：1999-07-13

申请号：US873502

申请日：1997-06-12

申请人： Emilio Yero

发明人： Emilio Yero

IPC分类号： G11C7/00 ,  G11C11/56 ,  G11C16/28 ,  G11C13/00

CPC分类号： G11C11/5642 ,  G11C11/56 ,  G11C11/5621 ,  G11C16/28 ,  G11C7/00 ,  G11C2211/5645 ,  G11C7/06

摘要： A device for the reading of cells for a memory includes a high-gain current comparison circuit, including a first arm for the reproduction, by current mirror, of the reference current conducted by a reference cell and a second arm for the reproduction, by current mirror, of the read current of a selected memory cell. A current mirror structure is provided to reproduce the current of the first arm in the second arm so as to obtain the comparison and produce a representative voltage level at output.

摘要翻译： 用于读取存储器单元的装置包括高增益电流比较电路，其包括第一臂，用于通过电流镜再现由参考单元传导的参考电流和用于再现的第二臂 反映所选存储单元的读取电流。 提供电流镜结构以再现第二臂中的第一臂的电流，以便获得比较并在输出时产生代表性的电压电平。

公开(公告)号：US5469382A

公开(公告)日：1995-11-21

申请号：US75524

申请日：1993-06-11

申请人： Emilio Yero

发明人： Emilio Yero

IPC分类号： G11C16/28 ,  G11C7/00

CPC分类号： G11C16/28

摘要： A device is provided for detecting the content of cells of a memory, and for minimizing the read access time of a high-capacity EPROM memory in which cells are organized as a set of bit rows. A comparator including a differential amplifier compares a reference current from a reference column with a read current invoked in a cell of a bit row. The reference current and a read current flow through a resistive reference element and a resistive read element respectively. These resistive elements are connected, at one end, to a supply voltage source and, at the other end, to the non-inverting input and the inverting input respectively of the differential amplifier. The differential amplifier delivers as output a detection signal. In a preloading period the output of the differential amplifier is connected to its inverting input.

摘要翻译： PCT No.PCT / FR92 / 00952 Sec。 371日期：1993年6月11日 102（e）日期1993年6月11日PCT提交1992年10月9日PCT公布。 出版物WO93 / 07622 日期为1993年4月15日。提供了一种用于检测存储器单元的内容并且用于最小化其中将单元组织为一组位行的高容量EPROM存储器的读取访问时间的设备。 包括差分放大器的比较器将来自参考列的参考电流与在位行的单元中调用的读取电流进行比较。 参考电流和读取电流分别通过电阻参考元件和电阻读取元件。 这些电阻元件的一端连接到电源电压源，另一端连接到差动放大器的非反相输入端和反相输入端。 差分放大器输出一个检测信号。 在预加载期间，差分放大器的输出端连接到其反相输入端。

公开(公告)号：US08180994B2

公开(公告)日：2012-05-15

申请号：US12499219

申请日：2009-07-08

申请人： Steven Sprouse ,  Jianmin Huang ,  Chris Avila ,  Yichao Huang ,  Emilio Yero

发明人： Steven Sprouse ,  Jianmin Huang ,  Chris Avila ,  Yichao Huang ,  Emilio Yero

IPC分类号： G06F12/00

CPC分类号： G11C11/5628 ,  G11C2211/5648

摘要： During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.

摘要翻译： 在非易失性存储系统中的编程数据传输过程中，数据的记录单元从主机传送到诸如存储卡的存储设备。 对于每个记录单元，数据页按照这样的顺序排列，使得在写入时间较少的页面之前提供需要更长时间写入存储器件的存储器阵列的页面。 由于发生更大程度的并行处理，记录单元的整体编程时间减少。 当将编程所需的时间更长的页面编程到存储器阵列时，将编程所需的较少时间的页面传送到存储器件。 编程完成后，存储器信号通知主机传送下一个记录单元。 数据页可以包括下页，中页和上页。

公开(公告)号：US08094492B2

公开(公告)日：2012-01-10

申请号：US12962902

申请日：2010-12-08

申请人： Dana Lee ,  Emilio Yero

发明人： Dana Lee ,  Emilio Yero

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

摘要翻译： 提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。 存储单元分为两个或更多个组。 在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。 在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。 在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。 在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。 在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

公开(公告)号：US20110075477A1

公开(公告)日：2011-03-31

申请号：US12962902

申请日：2010-12-08

申请人： Dana Lee ,  Emilio Yero

发明人： Dana Lee ,  Emilio Yero

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

摘要翻译： 提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。 存储单元分为两个或更多个组。 在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。 在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。 在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。 在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。 在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

公开(公告)号：US06418051B2

公开(公告)日：2002-07-09

申请号：US09785079

申请日：2001-02-14

申请人： Alessandro Manstretta ,  Rino Micheloni ,  Andrea Pierin ,  Emilio Yero

发明人： Alessandro Manstretta ,  Rino Micheloni ,  Andrea Pierin ,  Emilio Yero

IPC分类号： G11C1606

CPC分类号： G11C29/70

摘要： A non-volatile memory device with configurable row redundancy includes a non-volatile memory having a matrix of memory cells and a matrix of redundant memory cells, both organized into rows and columns. The memory device also includes row and column decoding circuits; read and modify circuits for reading and modifying data stored in the memory cells; and at least one associative memory matrix, also organized into rows and columns, able to store the addresses of faulty rows, and control circuits for controlling the associative memory matrix. The memory device further includes a circuit for recognizing and comparing selected row addresses with faulty row addresses contained in the associative memory matrix, such as to produce de-selection of the faulty row and selection of the corresponding redundant cell row in the event of a valid recognition; and a configuration register, also comprising a matrix of non-volatile memory cells, and associated control circuits.