公开(公告)号：US08687421B2

公开(公告)日：2014-04-01

申请号：US13435476

申请日：2012-03-30

申请人： Chris Avila ,  Jianmin Huang ,  Dana Lee

发明人： Chris Avila ,  Jianmin Huang ,  Dana Lee

IPC分类号： G11C16/00

CPC分类号： G06F11/1048 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/349 ,  G11C2211/5634

摘要： The decision on whether to refresh or retire a memory block is based on the set of dynamic read values being used. In a memory system using a table of dynamic read values, the table is configured to include how to handle read error (retire, refresh) in addition to the read parameters for the different dynamic read cases. In a refinement, the read case number can used to prioritize blocks selected for refresh or retire. In cases where the read scrub is to be made more precise, multiple dynamic read cases can be applied. Further, which cases are applied can be intelligently selected.

摘要翻译： 是否刷新或退出内存块的决定是基于正在使用的一组动态读取值。 在使用动态读取值表的存储器系统中，该表被配置为包括如何处理读取错误（退出，刷新）以及不同动态读取情况的读取参数。 在细化中，读取案例编号可用于对被选择进行刷新或退出的块进行优先级排序。 在读取擦除更精确的情况下，可以应用多个动态读取情况。 此外，可以智能地选择应用哪些情况。

公开(公告)号：US08634239B2

公开(公告)日：2014-01-21

申请号：US13339017

申请日：2011-12-28

申请人： Steven Sprouse ,  Chris Avila ,  Sergey Anatolievich Gorobets

发明人： Steven Sprouse ,  Chris Avila ,  Sergey Anatolievich Gorobets

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/10

摘要： A memory device implements hybrid programming sequences for writing data to multiple level cells (MLCs). The memory device obtains specified data to write to the MLC and selects among multiple different programming techniques to write the specified data. Each of the programming techniques establishes a charge configuration in the MLC that represents multiple data bits. The memory device writes the specified data to the MLC using the selected programming technique. In one implementation, the programming techniques include a robust programming technique that preserves previously written data in the MLC in the event of a write abort of the specified data and an additional programming technique that has higher average performance than the robust programming technique. The selection may be made based on a wide variety of criteria, including whether data has been previously written to a block that includes the MLC.

摘要翻译： 存储器件实现用于将数据写入多级单元（MLC）的混合编程序列。 存储器件获得指定的数据以写入MLC，并在多种不同的编程技术之间进行选择来写入指定的数据。 每个编程技术在MLC中建立代表多个数据位的电荷配置。 存储器件使用所选的编程技术将指定的数据写入MLC。 在一个实现中，编程技术包括鲁棒编程技术，其在写入中止指定数据的情况下保留MLC中的先前写入的数据，以及具有比鲁棒编程技术更高的平均性能的附加编程技术。 可以基于各种各样的标准来进行选择，包括数据是否已经被预先写入包括MLC的块。

公开(公告)号：US20130170293A1

公开(公告)日：2013-07-04

申请号：US13339017

申请日：2011-12-28

申请人： Steven Sprouse ,  Chris Avila ,  Sergey Anatolievich Gorobets

发明人： Steven Sprouse ,  Chris Avila ,  Sergey Anatolievich Gorobets

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/10

摘要： A memory device implements hybrid programming sequences for writing data to multiple level cells (MLCs). The memory device obtains specified data to write to the MLC and selects among multiple different programming techniques to write the specified data. Each of the programming techniques establishes a charge configuration in the MLC that represents multiple data bits. The memory device writes the specified data to the MLC using the selected programming technique. In one implementation, the programming techniques include a robust programming technique that preserves previously written data in the MLC in the event of a write abort of the specified data and an additional programming technique that has higher average performance than the robust programming technique. The selection may be made based on a wide variety of criteria, including whether data has been previously written to a block that includes the MLC.

摘要翻译： 存储器件实现用于将数据写入多级单元（MLC）的混合编程序列。 存储器件获得指定的数据以写入MLC，并在多种不同的编程技术之间进行选择来写入指定的数据。 每个编程技术在MLC中建立代表多个数据位的电荷配置。 存储器件使用所选的编程技术将指定的数据写入MLC。 在一个实现中，编程技术包括鲁棒编程技术，其在写入中止指定数据的情况下保留MLC中的先前写入的数据，以及具有比鲁棒编程技术更高的平均性能的附加编程技术。 可以基于各种各样的标准来进行选择，包括数据是否已经被预先写入包括MLC的块。

公开(公告)号：US08144512B2

公开(公告)日：2012-03-27

申请号：US12642649

申请日：2009-12-18

申请人： Jianmin Huang ,  Chris Avila ,  Lee M. Gavens ,  Neil David Hutchinson ,  Sergey Anatolievich Gorobets

发明人： Jianmin Huang ,  Chris Avila ,  Lee M. Gavens ,  Neil David Hutchinson ,  Sergey Anatolievich Gorobets

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G06F2212/7203 ,  G11C7/1042 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5643

摘要： A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read/write registers of the non-volatile memory circuit, and then written from the read/write registers to the first section of the non-volatile memory circuit using a binary write operation. Portions of the data and then subsequently folded from the first section of the non-volatile memory to the second section of the non-volatile memory, where a folding operation includes reading the portions of the data from multiple locations in the first section into the read/write registers and performing a multi-state programming operation of the portions of the data from the read/write registers into a location the second section of the non-volatile memory. The multi-state programming operations include a first phase and a second phase and one or more of the binary write operations are performed between the phases of the multi-state programming operations.

摘要翻译： 介绍了一种存储系统及其操作方法。 存储器系统包括易失性缓冲存储器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分，以及第二部分， 状态格式。 当将数据写入非易失性存储器时，将数据从存储在缓冲存储器中的主机接收，从缓冲存储器传送到非易失性存储器电路的读/写寄存器，然后从读/ 使用二进制写操作将寄存器写入非易失性存储器电路的第一部分。 然后将数据的部分随后从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括将第一部分中的多个位置的数据的部分读入读取 /写寄存器，并且将数据的部分的数据从读/写寄存器执行到非易失性存储器的第二部分的位置的多状态编程操作。 多状态编程操作包括第一阶段和第二阶段，并且在多状态编程操作的阶段之间执行二进制写入操作中的一个或多个。

公开(公告)号：US20110149650A1

公开(公告)日：2011-06-23

申请号：US12642649

申请日：2009-12-18

申请人： Jianmin Huang ,  Chris Avila ,  Lee M. Gavens ,  Neil David Hutchison ,  Sergey Anatolievich Gorobets

发明人： Jianmin Huang ,  Chris Avila ,  Lee M. Gavens ,  Neil David Hutchison ,  Sergey Anatolievich Gorobets

IPC分类号： G11C16/04 ,  G11C14/00

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G06F2212/7203 ,  G11C7/1042 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5643

摘要： A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read/write registers of the non-volatile memory circuit, and then written from the read/write registers to the first section of the non-volatile memory circuit using a binary write operation. Portions of the data and then subsequently folded from the first section of the non-volatile memory to the second section of the non-volatile memory, where a folding operation includes reading the portions of the data from multiple locations in the first section into the read/write registers and performing a multi-state programming operation of the potions of the data from the read/write registers into a location the second section of the non-volatile memory. The multi-state programming operations include a first phase and a second phase and one or more of the binary write operations are performed between the phases of the multi-state programming operations.

摘要翻译： 介绍了一种存储系统及其操作方法。 存储器系统包括易失性缓冲存储器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分，以及第二部分， 状态格式。 当将数据写入非易失性存储器时，将数据从存储在缓冲存储器中的主机接收，从缓冲存储器传送到非易失性存储器电路的读/写寄存器，然后从读/ 使用二进制写操作将寄存器写入非易失性存储器电路的第一部分。 然后将数据的部分随后从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括将第一部分中的多个位置的数据的部分读入读取 /写入寄存器，并且将数据从读/写寄存器执行到多状态编程操作到非易失性存储器的第二部分的位置。 多状态编程操作包括第一阶段和第二阶段，并且在多状态编程操作的阶段之间执行二进制写入操作中的一个或多个。

公开(公告)号：US09471419B2

公开(公告)日：2016-10-18

申请号：US13795470

申请日：2013-03-12

申请人： Abhijeet Manohar ,  Chris Avila

发明人： Abhijeet Manohar ,  Chris Avila

IPC分类号： G06F11/10 ,  G06F12/12 ,  G06F12/08 ,  G06F11/16

CPC分类号： G06F11/1469 ,  G06F11/1068 ,  G06F11/108 ,  G06F11/1451 ,  G06F11/16 ,  G06F12/0875 ,  G06F12/128 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2201/84 ,  G06F2212/222

摘要： Systems and methods for performing data recovery are disclosed. A controller of a memory system may detect an error at a first page of memory and identify a data keep cache associated with the first page, the data keep cache associated with a primary XOR sum. The controller may further sense data stored at a second page and move the data to a first latch of the memory; sense data stored at a third page such that the data is present in a second latch of the memory; and calculate a restoration XOR sum based on the data of the second page and the data of the third page. The controller may further calculate the data of the first page based on the primary XOR sum and the restoration XOR sum, and restore the data of the first page.

摘要翻译： 公开了用于执行数据恢复的系统和方法。 存储器系统的控制器可以检测存储器的第一页面上的错误，并且识别与第一页面相关联的数据保持缓存，数据保持高速缓存与主XOR和相关联。 控制器还可以感测存储在第二页面上的数据并将数据移动到存储器的第一锁存器; 感测存储在第三页的数据，使得数据存在于存储器的第二锁存器中; 并且基于第二页面的数据和第三页面的数据来计算恢复XOR和。 控制器还可以基于主XOR和还原XOR和计算第一页的数据，并恢复第一页的数据。

公开(公告)号：US09183081B2

公开(公告)日：2015-11-10

申请号：US13795460

申请日：2013-03-12

申请人： Abhijeet Manohar ,  Chris Avila ,  Jianmin Huang ,  Daniel Edward Tuers

发明人： Abhijeet Manohar ,  Chris Avila ,  Jianmin Huang ,  Daniel Edward Tuers

IPC分类号： G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  G11C29/04

CPC分类号： G06F11/1044 ,  G11C29/52 ,  G11C2029/0401 ,  G11C2029/0409 ,  G11C2029/0411

摘要： Systems and methods for performing defect detection and data recovery within a memory system are disclosed. A controller of a memory system may receive a command to write data in a memory of the memory system; determine a physical location of the memory that is associated with the data write; write data associated with the data write to the physical location; and store the physical location of the memory that is associated with the data write in a Tag cache. The controller may further identify a data keep cache of a plurality of data keep caches that is associated with the data write based on the physical location of the memory that is associated with the data write; update an XOR sum based on the data of the data write; and store the updated XOR sum in the identified data keep cache.

摘要翻译： 公开了用于在存储器系统内执行缺陷检测和数据恢复的系统和方法。 存储器系统的控制器可以接收在存储器系统的存储器中写入数据的命令; 确定与数据写入相关联的存储器的物理位置; 将与数据相关联的数据写入物理位置; 并将与数据写入相关联的存储器的物理位置存储在标签高速缓存中。 控制器可以基于与数据写入相关联的存储器的物理位置，进一步识别与数据写入相关联的多个数据保持高速缓存的数据保持高速缓存; 基于数据写入的数据更新XOR和; 并将更新的XOR和存储在所识别的数据保持缓存中。

公开(公告)号：US20140281250A1

公开(公告)日：2014-09-18

申请号：US13795470

申请日：2013-03-12

申请人： Abhijeet Manohar ,  Chris Avila

发明人： Abhijeet Manohar ,  Chris Avila

IPC分类号： G06F12/12

CPC分类号： G06F11/1469 ,  G06F11/1068 ,  G06F11/108 ,  G06F11/1451 ,  G06F11/16 ,  G06F12/0875 ,  G06F12/128 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2201/84 ,  G06F2212/222

摘要： Systems and methods for performing data recovery are disclosed. A controller of a memory system may detect an error at a first page of memory and identify a data keep cache associated with the first page, the data keep cache associated with a primary XOR sum. The controller may further sense data stored at a second page and move the data to a first latch of the memory; sense data stored at a third page such that the data is present in a second latch of the memory; and calculate a restoration XOR sum based on the data of the second page and the data of the third page. The controller may further calculate the data of the first page based on the primary XOR sum and the restoration XOR sum, and restore the data of the first page.

摘要翻译： 公开了用于执行数据恢复的系统和方法。 存储器系统的控制器可以检测存储器的第一页面上的错误，并且识别与第一页面相关联的数据保持缓存，数据保持高速缓存与主XOR和相关联。 控制器还可以感测存储在第二页面上的数据并将数据移动到存储器的第一锁存器; 感测存储在第三页的数据，使得数据存在于存储器的第二锁存器中; 并且基于第二页面的数据和第三页面的数据来计算恢复XOR和。 控制器还可以基于主XOR和还原XOR和计算第一页的数据，并恢复第一页的数据。

公开(公告)号：US20130205066A1

公开(公告)日：2013-08-08

申请号：US13365595

申请日：2012-02-03

申请人： Gautam A. Dusija ,  Jianmin Huang ,  Chris Avila

发明人： Gautam A. Dusija ,  Jianmin Huang ,  Chris Avila

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/7202

摘要： A memory system or flash card may include safe zone blocks where data is written in case of an error condition, such as a write abort. The system may utilize predetermined risk zones when selecting the data that is written to the safe zone blocks. For example, data written to a lower page may be one example of data that is a predetermined risk. Upon receiving a write command, the data that is written to a lower page may be written to a safe zone either in parallel or after the write operation.

摘要翻译： 存储器系统或闪存卡可以包括在诸如写中止的错误状况的情况下写入数据的安全区块块。 当选择写入安全区块的数据时，系统可以利用预定的风险区域。 例如，写入下页的数据可以是预定风险的数据的一个示例。 一旦接收到写入命令，写入下一页的数据可以并行地或写入操作之后被写入安全区域。

公开(公告)号：US20130166893A1

公开(公告)日：2013-06-27

申请号：US13336223

申请日：2011-12-23

申请人： Gautam A. Dusija ,  Jianmin Huang ,  Chris Avila

发明人： Gautam A. Dusija ,  Jianmin Huang ,  Chris Avila

IPC分类号： G06F9/445

CPC分类号： G06F11/1068 ,  G06F8/654

摘要： A memory system or flash card may be initialized from a protected block of flash memory as a backup process. If there is an error during regular card initialization and the firmware for the card cannot be loaded, the card may be inaccessible to a user. Booting with a protected block of memory may be used to load a different version of the firmware that can still initialize the card despite the error from loading the other firmware.

摘要翻译： 存储器系统或闪存卡可以从受保护的闪存块作为备份过程被初始化。 如果在普通卡初始化期间发生错误，并且无法加载卡的固件，则卡可能无法访问用户。 使用受保护的内存块引导可以用于加载仍然可以初始化卡的固件的不同版本，尽管加载其他固件存在错误。