公开(公告)号：US08184479B2

公开(公告)日：2012-05-22

申请号：US13221147

申请日：2011-08-30

申请人： Dana Lee ,  Emilio Yero

发明人： Dana Lee ,  Emilio Yero

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

公开(公告)号：US07577037B2

公开(公告)日：2009-08-18

申请号：US11619513

申请日：2007-01-03

申请人： Yan Li ,  Emilio Yero

发明人： Yan Li ,  Emilio Yero

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/22 ,  G11C16/04 ,  G11C2207/2245 ,  Y02D10/13

摘要： Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

摘要翻译： 存在用于通过允许具有相同存储器的操作的相间流水线来提高非易失性存储器件中的性能的方法和电路，从而允许在写入操作的脉冲和验证阶段之间交错读取操作。 在示例性实施例中，两个操作共享数据锁存器。 在具体示例中，在多级写入操作中的验证所需的数据锁存器中，它们可用于存储在多级写入中的步骤之间执行的读取期间从另一位置读取的数据。 在示例性实施例中，多级写入仅需要暂停，执行读取，并在暂停点恢复写入。

公开(公告)号：US20090059660A1

公开(公告)日：2009-03-05

申请号：US11849992

申请日：2007-09-04

申请人： Dana Lee ,  Emilio Yero

发明人： Dana Lee ,  Emilio Yero

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

摘要翻译： 提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。 存储单元分为两个或更多个组。 在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。 在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。 在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。 在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。 在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

公开(公告)号：US20070109867A1

公开(公告)日：2007-05-17

申请号：US11619513

申请日：2007-01-03

申请人： Yan Li ,  Emilio Yero

发明人： Yan Li ,  Emilio Yero

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/22 ,  G11C16/04 ,  G11C2207/2245 ,  Y02D10/13

摘要： Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

摘要翻译： 存在用于通过允许具有相同存储器的操作的相间流水线来提高非易失性存储器件中的性能的方法和电路，从而允许在写入操作的脉冲和验证阶段之间交错读取操作。 在示例性实施例中，两个操作共享数据锁存器。 在具体示例中，在多级写入操作中的验证所需的数据锁存器中，它们可用于存储在多级写入中的步骤之间执行的读取期间从另一位置读取的数据。 在示例性实施例中，多级写入仅需要暂停，执行读取，并在暂停点恢复写入。

公开(公告)号：US5699295A

公开(公告)日：1997-12-16

申请号：US649282

申请日：1996-05-17

申请人： Emilio Yero

发明人： Emilio Yero

IPC分类号： G11C11/41 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00 ,  G11C7/06

CPC分类号： G11C16/28 ,  G11C7/14

摘要： In a memory in integrated circuit form, organized as a matrix of rows and columns, a current detection circuit is connected at input to at least one column of the memory and at output to a corresponding read circuit. The current detection circuit includes a transistor connected between the input and the output and controlled at its gate by a reference current detection circuit.

摘要翻译： 在集成电路形式的存储器中，组织成行和列的矩阵，电流检测电路在输入端连接到存储器的至少一列并输出到对应的读取电路。 电流检测电路包括连接在输入和输出端之间的晶体管，并通过参考电流检测电路在其栅极处控制。

公开(公告)号：US20110310671A1

公开(公告)日：2011-12-22

申请号：US13221147

申请日：2011-08-30

申请人： Dana Lee ,  Emilio Yero

发明人： Dana Lee ,  Emilio Yero

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

公开(公告)号：US07869273B2

公开(公告)日：2011-01-11

申请号：US11849992

申请日：2007-09-04

申请人： Dana Lee ,  Emilio Yero

发明人： Dana Lee ,  Emilio Yero

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

摘要翻译： 提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。 存储单元分为两个或更多个组。 在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。 在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。 在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。 在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。 在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

公开(公告)号：US07451264B2

公开(公告)日：2008-11-11

申请号：US11404672

申请日：2006-04-13

申请人： Emilio Yero

发明人： Emilio Yero

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A hot count records the number of erase operations experienced by a block. The hot count is stored in an overhead data area of the block and is updated by circuits located on the same substrate as the block. Where a memory has two or more planes, each plane has circuits for updating hot counts.

摘要翻译： 热计数记录块所经历的擦除操作的数量。 热计数存储在块的开销数据区域中，并且通过位于与块相同的衬底上的电路来更新。 在存储器具有两个或更多个平面的情况下，每个平面具有用于更新热计数的电路。

公开(公告)号：US20070245068A1

公开(公告)日：2007-10-18

申请号：US11404672

申请日：2006-04-13

申请人： Emilio Yero

发明人： Emilio Yero

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A hot count records the number of erase operations experienced by a block. The hot count is stored in an overhead data area of the block and is updated by circuits located on the same substrate as the block. Where a memory has two or more planes, each plane has circuits for updating hot counts.

摘要翻译： 热计数记录块所经历的擦除操作的数量。 热计数存储在块的开销数据区域中，并且通过位于与块相同的衬底上的电路来更新。 在存储器具有两个或更多个平面的情况下，每个平面具有用于更新热计数的电路。

公开(公告)号：US06140876A

公开(公告)日：2000-10-31

申请号：US188071

申请日：1998-11-06

申请人： Emilio Yero

发明人： Emilio Yero

IPC分类号： H03F3/45

CPC分类号： H03F3/4565 ,  H03F3/45183 ,  H03F3/45659 ,  H03F2203/45112 ,  H03F2203/45648

摘要： In a differential amplifier with asymmetrical outputs, the gates of the two load transistors are at the same specified potential and the voltage at the connection node between the load transistor and the amplifier transistor of one arm is stabilized by means of a compensation structure. This amplifier works at low VCC (e.g., less than 2 volts) while at the same time having high gain.

摘要翻译： 在具有不对称输出的差分放大器中，两个负载晶体管的栅极处于相同的指定电位，负载晶体管和一个臂的放大器晶体管之间的连接节点处的电压通过补偿结构来稳定。 该放大器工作在低VCC（例如，小于2伏特），同时具有高增益。