公开(公告)号：US08093665B2

公开(公告)日：2012-01-10

申请号：US12467479

申请日：2009-05-18

申请人： I-Chen Yang ,  Guan-Wei Wu ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： I-Chen Yang ,  Guan-Wei Wu ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/66636 ,  H01L29/665 ,  H01L29/7834

摘要： A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is disposed on the first surface. The doped regions are configured in the substrate at both sides of the gate structure and under the second surface. The lightly doped regions are configured in the substrate between the gate structure and the doped regions, respectively. Each lightly doped region includes a first part and a second part connecting with each other. The first part is disposed under the second surface, and the second part is disposed under the third surface.

摘要翻译： 描述了一种半导体器件，其包括衬底，栅极结构，掺杂区域和轻掺杂区域。 基板具有阶梯状的上表面，其包括第一表面，第二表面和第三表面。 第二表面低于第一表面。 第三表面连接第一表面和第二表面。 栅极结构设置在第一表面上。 掺杂区域在栅极结构的两侧和第二表面的下方在衬底中配置。 轻掺杂区域分别配置在栅极结构和掺杂区域之间的衬底中。 每个轻掺杂区域包括彼此连接的第一部分和第二部分。 第一部分设置在第二表面下方，第二部分设置在第三表面下。

公开(公告)号：US20110080784A1

公开(公告)日：2011-04-07

申请号：US12574093

申请日：2009-10-06

申请人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10

CPC分类号： G11C16/3468 ,  G11C16/0466 ,  G11C16/10

摘要： An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting N threshold-voltage distribution curves, wherein the N threshold-voltage distribution curves correspond to N levels and N is an integer greater than 2; programming the first and the second storage positions to the 1st level and an auxiliary level respectively according to the 1st threshold-voltage distribution curve and a threshold-voltage auxiliary curve when the first and the second storage positions are programmed to the 1st and Nth levels; and programming the first and the second storage positions to the ith level according to the ith threshold-voltage distribution curve when the first and the second storage positions are not to be programmed to the 1st and Nth levels, wherein i is an integer and 1≦i≦N.

摘要翻译： 提供适用于具有第一存储位置和第二存储位置的多级单元的非易失性存储器的操作方法。 操作方法包括：设置N个阈值电压分布曲线，其中N个阈值电压分布曲线对应于N个电平，N是大于2的整数; 当第一和第二存储位置被编程到第1和第N级时，根据第一阈值电压分布曲线和阈值电压辅助曲线分别将第一和第二存储位置编程到第一级和辅助级; 以及当所述第一和第二存储位置不被编程到所述第一和第N电平时，根据所述第i阈值电压分布曲线将所述第一和第二存储位置编程为第i级，其中i是整数和1＆nlE; 我＆nlE; N。

公开(公告)号：US20100314680A1

公开(公告)日：2010-12-16

申请号：US12862020

申请日：2010-08-24

申请人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L21/76885 ,  H01L27/11568 ,  H01L29/4234

摘要： A memory array includes a charge storage structure and a plurality of conductive materials over the charge storage structure is provided. Each conductive material, serving as a word line, has a substantially arc-sidewall and a substantially straight sidewall.

摘要翻译： 存储器阵列包括电荷存储结构，并且提供了电荷存储结构上的多个导电材料。 用作字线的每个导电材料具有基本上弧形的侧壁和基本上直的侧壁。

公开(公告)号：US07830707B2

公开(公告)日：2010-11-09

申请号：US11905211

申请日：2007-09-28

申请人： Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C16/28

摘要： A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage node near the first terminal and the second terminal respectively. First, a controlling voltage and a read voltage are applied to the controlling terminal and the first terminal respectively. The second terminal is grounded to measure a first output current value of the first terminal. Then, the controlling voltage and the read voltage are applied to the controlling terminal and the second terminal respectively. The first terminal is grounded to measure a second output current value of the second terminal. Afterward, the bit state of the first bit storage node and the bit state of the second bit storage node is read simultaneously according to the first output current value and the second output current value.

摘要翻译： 读取双位存储单元的方法包括控制终端，第一终端和第二终端。 双位存储单元分别具有第一位存储节点和靠近第一终端和第二终端的第二位存储节点。 首先，分别对控制端子和第一端子施加控制电压和读取电压。 第二端子接地以测量第一端子的第一输出电流值。 然后，控制电压和读取电压分别施加到控制端子和第二端子。 第一端子接地以测量第二端子的第二输出电流值。 之后，根据第一输出电流值和第二输出电流值同时读取第一位存储节点的位状态和第二位存储节点的位状态。

公开(公告)号：US07692968B2

公开(公告)日：2010-04-06

申请号：US11782149

申请日：2007-07-24

申请人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

IPC分类号： G11C11/34

CPC分类号： G11C16/0466 ,  G11C16/26

摘要： An operation method of a non-volatile memory is provided. The operation method is that a reading operation is performed to a selected nitride-based memory cell, a first positive voltage is applied to a word line adjacent to one side of the selected memory cell and a second positive voltage is applied to another word line adjacent to the other side of the selected memory cell. The operation method of this present invention not only can reduce a coupling interference issue but also can obtain a wider operation window.

摘要翻译： 提供了一种非易失性存储器的操作方法。 操作方法是对所选择的基于氮化物的存储单元执行读取操作，将第一正电压施加到与所选存储单元的一侧相邻的字线，并且将第二正电压施加到相邻的另一个字线 到所选存储单元的另一侧。 本发明的操作方法不仅可以减少耦合干扰问题，而且可以获得更宽的操作窗口。

公开(公告)号：US06683352B2

公开(公告)日：2004-01-27

申请号：US10078314

申请日：2002-02-15

申请人： Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L2976

CPC分类号： H01L21/823425 ,  H01L21/823443 ,  H01L29/4238 ,  H01L29/665

摘要： A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate and the semiconductor substrate. A drain region is disposed within the semiconductor substrate, wherein the drain region is surrounded by the p-shape gate. A source region is disposed within the semiconductor substrate, wherein the source region surrounds the p-shape gate. A silicide structure is disposed on the source/drain regions and the p-shape gate.

摘要翻译： 公开了一种金属氧化物半导体场效应晶体管结构。 p型栅极，设置在半导体衬底上。 栅极电介质层设置在p型栅极和半导体衬底之间。 漏极区域设置在半导体衬底内，其中漏极区域被p型栅极包围。 源极区域设置在半导体衬底内，其中源极区域围绕p形栅极。 在源极/漏极区域和p形栅极上设置硅化物结构。

公开(公告)号：US06549029B1

公开(公告)日：2003-04-15

申请号：US09990261

申请日：2001-11-20

申请人： Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G01R3126

CPC分类号： G01R27/2605

摘要： A circuit structure for measuring a capacitive load. The capacitive load is coupled between a first and a second nodes, and drains of a first PMOS and a first NMOS transistors are coupled to the first node, and drains of a second PMOS and a second NMOS transistors are coupled to the second node, and a pad is coupled to the second node. First, sources of the first and the second PMOS transistors and sources of the first and the second NMOS transistors are biased at a power source and a ground respectively. A non-synchronized voltage is applied to gates of the first and the second PMOS transistors and to gates of the first and the second NMOS transistors simultaneously. By grounding and floating the pad, a current flowing through the capacitive load is obtained to calculate the capacitance.

摘要翻译： 用于测量电容性负载的电路结构。 电容性负载耦合在第一和第二节点之间，并且第一PMOS和第一NMOS晶体管的漏极耦合到第一节点，并且第二PMOS和第二NMOS晶体管的漏极耦合到第二节点，并且 垫连接到第二节点。 首先，第一和第二PMOS晶体管的源极和第一和第二NMOS晶体管的源极分别偏置在电源和地。 非同步电压同时施加到第一和第二PMOS晶体管的栅极和第一和第二NMOS晶体管的栅极。 通过接地和浮动焊盘，获得流过电容性负载的电流来计算电容。

公开(公告)号：US08014203B2

公开(公告)日：2011-09-06

申请号：US12614647

申请日：2009-11-09

申请人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu ,  Guan-Wei Wu ,  Tao-Yuan Lin ,  Po-Chou Chen

发明人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu ,  Guan-Wei Wu ,  Tao-Yuan Lin ,  Po-Chou Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

摘要： The memory device is described, which includes a substrate, a conductive layer, a plurality of charge storage layers and a plurality of doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layers are disposed between the substrate and the conductive layer in the trenches respectively, wherein the charge storage layers are separated from each other. The doped regions are configured in the substrate under bottoms of the trenches, respectively.

摘要翻译： 描述了存储器件，其包括衬底，导电层，多个电荷存储层和多个掺杂区域。 衬底具有形成在其中的多个沟槽。 导电层设置在基板上并填充沟槽。 电荷存储层分别设置在沟槽中的衬底和导电层之间，其中电荷存储层彼此分离。 掺杂区域分别配置在沟槽底部的衬底中。

公开(公告)号：US20110038208A1

公开(公告)日：2011-02-17

申请号：US12914020

申请日：2010-10-28

申请人： Yao-Wen CHANG ,  Tao-Cheng Lu

发明人： Yao-Wen CHANG ,  Tao-Cheng Lu

IPC分类号： G11C16/26 ,  G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/28

摘要： A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage node near the first terminal and the second terminal respectively. First, a controlling voltage and a read voltage are applied to the controlling terminal and the first terminal respectively. The second terminal is grounded to measure a first output current value of the first terminal. Then, the controlling voltage and the read voltage are applied to the controlling terminal and the second terminal respectively. The first terminal is grounded to measure a second output current value of the second terminal. Afterward, the bit state of the first bit storage node and the bit state of the second bit storage node is read simultaneously according to the first output current value and the second output current value.

摘要翻译： 读取双位存储单元的方法包括控制终端，第一终端和第二终端。 双位存储单元分别具有第一位存储节点和靠近第一终端和第二终端的第二位存储节点。 首先，分别对控制端子和第一端子施加控制电压和读取电压。 第二端子接地以测量第一端子的第一输出电流值。 然后，控制电压和读取电压分别施加到控制端子和第二端子。 第一端子接地以测量第二端子的第二输出电流值。 之后，根据第一输出电流值和第二输出电流值同时读取第一位存储节点的位状态和第二位存储节点的位状态。

公开(公告)号：US20100112797A1

公开(公告)日：2010-05-06

申请号：US12263091

申请日：2008-10-31

申请人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L21/3205

CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  Y10S438/954

摘要： The invention is directed to a method for forming a memory array. The method comprises steps of providing a substrate having a charge trapping structure formed thereon. A patterned material layer is formed over the substrate and the patterned material layer having a plurality of trenches expose a portion of the charge trapping structure. Furthermore, a plurality of conductive spacers are formed on the sidewalls of the trenches of the patterned material layer respectively and a portion of the charge trapping structure at the bottom of the trenches is exposed by the conductive spacers. An insulating layer is formed over the substrate to fill up the trenches of the patterned material layer. Moreover, a planarization process is performed to remove a portion of the insulating layer until a top surface of the patterned material layer and a top surface of each of the conductive spacers are exposed.

摘要翻译： 本发明涉及一种用于形成存储器阵列的方法。 该方法包括提供其上形成有电荷捕获结构的衬底的步骤。 图案化的材料层形成在衬底上，并且具有多个沟槽的图案化材料层暴露电荷俘获结构的一部分。 此外，在图案化材料层的沟槽的侧壁上分别形成多个导电间隔物，并且沟槽底部的电荷捕获结构的一部分被导电间隔物暴露。 在衬底上形成绝缘层以填充图案化材料层的沟槽。 此外，执行平面化处理以去除绝缘层的一部分，直到图案化材料层的顶表面和每个导电间隔物的顶表面露出。