公开(公告)号：US20080150013A1

公开(公告)日：2008-06-26

申请号：US11644344

申请日：2006-12-22

申请人： Sung-Shan Tai ,  Yong-Zhong Hu ,  Francois Hebert ,  Hong Chang ,  Mengyu Pan ,  Yingying Lou ,  Yu Wang

发明人： Sung-Shan Tai ,  Yong-Zhong Hu ,  Francois Hebert ,  Hong Chang ,  Mengyu Pan ,  Yingying Lou ,  Yu Wang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/66734

摘要： This invention discloses method of for manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.

摘要翻译： 本发明公开了一种制造半导体功率器件的方法，该沟槽半导体功率器件具有填充在半导体衬底中开口的沟槽的分离栅极，其中，分离栅极由设置在顶部和底部栅极段之间的多晶硅绝缘层分开。 该方法还包括通过在HDP氧化物沉积工艺之后施加RTP工艺以形成HDP氧化物层的蚀刻速率接近热氧化物的蚀刻速率来形成多晶硅层之间的步骤。

公开(公告)号：US08008151B2

公开(公告)日：2011-08-30

申请号：US11983769

申请日：2007-11-09

申请人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

发明人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.

摘要翻译： 一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量 延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

公开(公告)号：US20110198588A1

公开(公告)日：2011-08-18

申请号：US13066583

申请日：2011-04-18

申请人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

发明人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L22/12 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

摘要翻译： 本发明公开了一种用于在其上制造电子电路的半导体晶片。 半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部 具有较小的平面沟槽尺寸。

公开(公告)号：US20100084707A1

公开(公告)日：2010-04-08

申请号：US12653130

申请日：2009-12-09

申请人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

发明人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

IPC分类号： H01L29/78 ,  H01L23/544 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L22/12 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

摘要翻译： 本发明公开了一种用于在其上制造电子电路的半导体晶片。 半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部 具有较小的平面沟槽尺寸。

公开(公告)号：US20080090357A1

公开(公告)日：2008-04-17

申请号：US11983769

申请日：2007-11-09

申请人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

发明人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.

摘要翻译： 一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量 延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

公开(公告)号：US20070075360A1

公开(公告)日：2007-04-05

申请号：US11240255

申请日：2005-09-30

申请人： Hong Chang ,  Tiesheng Li ,  Sung-Shan Tai ,  Daniel Ng ,  Anup Bhalla

发明人： Hong Chang ,  Tiesheng Li ,  Sung-Shan Tai ,  Daniel Ng ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66734 ,  H01L29/7811

摘要： This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) cell that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a source contact opening opened on top of an area extended over the body region and the source region through a protective insulation layer wherein the area further has a cobalt-silicide layer disposed near a top surface of the substrate. The MOSFET cell further includes a Ti/TiN conductive layer covering the area interfacing with the cobalt-silicide layer over the source contact opening. The MOSFET cell further includes a source contact metal layer formed on top of the Ti/TiN conductive layer ready to form source-bonding wires thereon.

摘要翻译： 本发明公开了一种改进的沟槽金属氧化物半导体场效应晶体管（MOSFET）单元，其包括被包围在设置在基板的底表面上的漏极区域上方的体区域中的源极区域包围的沟槽栅极。 MOSFET单元进一步包括源极接触开口，该开口位于通过保护绝缘层延伸到主体区域上的区域的顶部，并且源区域通过保护绝缘层开放，其中该区域还具有设置在基板顶表面附近的硅化钴层。 MOSFET单元还包括覆盖源极接触开口上与硅化钴层接合的区域的Ti / TiN导电层。 MOSFET单元还包括形成在Ti / TiN导电层的顶部上的源极接触金属层，准备在其上形成源极接合线。

公开(公告)号：US07932148B2

公开(公告)日：2011-04-26

申请号：US12378040

申请日：2009-02-09

申请人： Hong Chang ,  Sung-Shan Tai ,  Tiesheng Li ,  Yu Wang

发明人： Hong Chang ,  Sung-Shan Tai ,  Tiesheng Li ,  Yu Wang

IPC分类号： H01L21/336

CPC分类号： H01L21/76232 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/7834

摘要： This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric liner layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate. The MOSFET device has a reduced gate to drain capacitance Cgd depending on the controllable depth of the trenched gate disposed above the SGT structure formed as a round hole below the trenched gate.

摘要翻译： 本发明公开了一种改进的沟槽金属氧化物半导体场效应晶体管（MOSFET）器件，其包括被包围在设置在衬底的底表面上的漏区以上的体区中的源极区包围的沟槽栅。 MOSFET单元进一步包括屏蔽栅极沟槽（SGT）结构，并且与沟槽栅极绝缘。 SGT结构基本上形成为具有延伸超过沟槽栅极并且被填充有沟槽栅极材料的介电衬垫层覆盖的横向膨胀的圆孔。 圆形孔通过在沟槽底部的各向同性蚀刻形成，并且通过氧化物绝缘层与沟槽栅极绝缘。 圆孔具有超出沟槽壁的横向膨胀，并且横向膨胀用作用于控制沟槽浇口的深度的垂直对准界标。 MOSFET器件具有减小的栅极到漏极电容Cgd，这取决于设置在形成为沟槽栅极下方的圆孔的SGT结构之上的沟槽栅极的可控深度。

公开(公告)号：US07492005B2

公开(公告)日：2009-02-17

申请号：US11321957

申请日：2005-12-28

申请人： Hong Chang ,  Sung-Shan Tai ,  Tiesheng Li ,  Yu Wang

发明人： Hong Chang ,  Sung-Shan Tai ,  Tiesheng Li ,  Yu Wang

IPC分类号： H01L29/76

CPC分类号： H01L21/76232 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/7834

摘要： This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric liner layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate. The MOSFET device has a reduced gate to drain capacitance Cgd depending on the controllable depth of the trenched gate disposed above the SGT structure formed as a round hole below the trenched gate.

摘要翻译： 本发明公开了一种改进的沟槽金属氧化物半导体场效应晶体管（MOSFET）器件，其包括被包围在设置在衬底的底表面上的漏区以上的体区中的源极区包围的沟槽栅极。 MOSFET单元进一步包括屏蔽栅极沟槽（SGT）结构，并且与沟槽栅极绝缘。 SGT结构基本上形成为具有延伸超过沟槽栅极并且被填充有沟槽栅极材料的介电衬垫层覆盖的横向膨胀的圆孔。 圆形孔通过在沟槽底部的各向同性蚀刻形成，并且通过氧化物绝缘层与沟槽栅极绝缘。 圆孔具有超出沟槽壁的横向膨胀，并且横向膨胀用作用于控制沟槽浇口的深度的垂直对准界标。 MOSFET器件具有减小的栅极到漏极电容Cgd，这取决于设置在形成为沟槽栅极下方的圆孔的SGT结构之上的沟槽栅极的可控深度。

公开(公告)号：US20060071268A1

公开(公告)日：2006-04-06

申请号：US10952231

申请日：2004-09-27

申请人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

发明人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device comprises a drain, a body in contact with the drain, the body having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a trench extending through the source and the body to the drain, and a gate disposed in the trench, having a gate top surface that extends substantially above the body top surface. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.

摘要翻译： 半导体器件包括漏极，与漏极接触的主体，主体具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中，延伸穿过源和主体的沟槽 并且设置在沟槽中的门具有大致在主体顶表面上方延伸的门顶表面。 一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量 延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

公开(公告)号：US20120193631A1

公开(公告)日：2012-08-02

申请号：US13431551

申请日：2012-03-27

申请人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

发明人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L22/12 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

摘要翻译： 本发明公开了一种用于在其上制造电子电路的半导体晶片。 半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部 具有较小的平面沟槽尺寸。