公开(公告)号：US20130320398A1

公开(公告)日：2013-12-05

申请号：US13483322

申请日：2012-05-30

申请人： Da-Wei Lai

发明人： Da-Wei Lai

IPC分类号： H01L21/332 ,  H01L29/74

CPC分类号： H01L29/744 ,  H01L27/0262 ,  H01L27/0641 ,  H01L28/20 ,  H01L28/40 ,  H01L29/1012 ,  H01L29/7436

摘要： An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad.

公开(公告)号：US20110051298A1

公开(公告)日：2011-03-03

申请号：US12548586

申请日：2009-08-27

申请人： Da-Wei Lai

发明人： Da-Wei Lai

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： In some embodiments, an electrostatic discharge (ESD) protection circuit includes a substrate resistance control circuit coupled to a body of a first NMOS transistor. The substrate resistance control circuit increases a resistance of the body of the first NMOS transistor during an ESD event. The first NMOS transistor has a drain coupled to an input/output (I/O) pad and a gate coupled to a first voltage source. The first voltage source is set at ground potential.

摘要翻译： 在一些实施例中，静电放电（ESD）保护电路包括耦合到第一NMOS晶体管的主体的衬底电阻控制电路。 衬底电阻控制电路在ESD事件期间增加了第一NMOS晶体管的主体的电阻。 第一NMOS晶体管具有耦合到输入/输出（I / O）焊盘和耦合到第一电压源的栅极的漏极。 第一个电压源设置在地电位。

公开(公告)号：US08913359B2

公开(公告)日：2014-12-16

申请号：US13710700

申请日：2012-12-11

申请人： Da-Wei Lai ,  Ying-Chang Lin ,  Handoko Linewih

发明人： Da-Wei Lai ,  Ying-Chang Lin ,  Handoko Linewih

IPC分类号： H02H3/22 ,  H02H9/04

CPC分类号： H02H9/044 ,  H01L27/0274 ,  H01L27/0277 ,  H02H9/046

摘要： An RC-based electrostatic discharge protection device provides an extended snapback trigger voltage range, thereby avoiding latch-up. Two parallel current discharge paths are provided between supply terminals during an electrostatic discharge event by virtue of an added external resistor. The first current discharge path includes body resistance of the protection device and the second current discharge path includes the external resistor.

摘要翻译： 基于RC的静电放电保护装置提供扩展的快速恢复触发电压范围，从而避免闩锁。 在静电放电事件期间，通过附加的外部电阻器，在电源端子之间提供两个并联电流放电路径。 第一电流放电路径包括保护装置的体电阻，第二电流放电路径包括外部电阻器。

公开(公告)号：US08891215B2

公开(公告)日：2014-11-18

申请号：US13711141

申请日：2012-12-11

申请人： Da-Wei Lai ,  Handoko Linewih ,  Ying-Chang Lin

发明人： Da-Wei Lai ,  Handoko Linewih ,  Ying-Chang Lin

IPC分类号： H02H9/00 ,  H02H9/04 ,  H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22

CPC分类号： H02H9/04 ,  H01L27/0274 ,  H01L27/0285 ,  H02H9/043 ,  H02H9/046 ,  Y10T29/49117

摘要： A triple stack NMOS integrated circuit structure protection circuit for a plurality of terminals operative at respective voltage levels is coupled between the plurality of terminals. First and second NMOS elements of the triple stack NMOS share a common active region. A third NMOS element, vertically positioned with respect to the first and second NMOS elements, has an active region separate from the active region of the first and second NMOS elements. The first, second and third NMOS elements are connected in series between two terminals of the plurality of terminals.

摘要翻译： 用于在各个电压电平下工作的多个终端的三重堆叠的NMOS集成电路结构保护电路耦合在多个终端之间。 三重堆叠NMOS的第一和第二NMOS元件共享公共有源区。 相对于第一和第二NMOS元件垂直定位的第三NMOS元件具有与第一和第二NMOS元件的有源区分离的有源区。 第一，第二和第三NMOS元件串联连接在多个端子的两个端子之间。

公开(公告)号：US08848326B2

公开(公告)日：2014-09-30

申请号：US13415970

申请日：2012-03-09

申请人： Da-Wei Lai ,  Ying-Chang Lin

发明人： Da-Wei Lai ,  Ying-Chang Lin

IPC分类号： H02H9/00

CPC分类号： H03K19/00315 ,  H01L27/0292 ,  H01L2924/0002 ,  H01L2924/00

摘要： A cross-domain ESD protection scheme is disclosed. Embodiments include coupling a first power clamp to a first power rail and a first ground rail; providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source to a second ground rail; providing a first PMOS transistor having a second source, a second drain, and a second gate; coupling the second source to the first power rail; and providing, via the first power clamp, a signal to turn on the first NMOS transistor during an ESD event that occurs at the first power rail.

摘要翻译： 公开了跨域ESD保护方案。 实施例包括将第一电力钳夹连接到第一电力轨和第一接地轨; 提供具有第一源极，第一漏极和第一栅极的第一NMOS晶体管; 将第一源耦合到第二接地导轨; 提供具有第二源极，第二漏极和第二栅极的第一PMOS晶体管; 将第二源耦合到第一电力轨; 以及经由所述第一功率钳位件在发生在所述第一电力轨道处的ESD事件期间提供用于接通所述第一NMOS晶体管的信号。

公开(公告)号：US08792219B2

公开(公告)日：2014-07-29

申请号：US13482423

申请日：2012-05-29

申请人： Da-Wei Lai ,  Ying-Chang Lin

发明人： Da-Wei Lai ,  Ying-Chang Lin

IPC分类号： H02H3/22

CPC分类号： H01L27/0292 ,  H01L2924/0002 ,  H02H9/046 ,  H01L2924/00

摘要： An ESD-robust I/O driver circuit is disclosed. Embodiments include providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source is coupled to a ground rail, and the first drain to an I/O pad; providing a gate driver control circuit including a second NMOS transistor having a second source, a second drain, and a second gate; and coupling the second drain to the first gate, the second source to the ground rail, wherein the gate driver control circuit provides a ground potential to the first gate during an ESD event occurring from the I/O pad to the ground rail.

摘要翻译： 公开了一种ESD稳健的I / O驱动器电路。 实施例包括提供具有第一源极，第一漏极和第一栅极的第一NMOS晶体管; 耦合第一源耦合到接地导轨，并且第一漏极耦合到I / O焊盘; 提供包括具有第二源极，第二漏极和第二栅极的第二NMOS晶体管的栅极驱动器控制电路; 以及将所述第二漏极耦合到所述第一栅极，所述第二源极耦合到所述接地导轨，其中所述栅极驱动器控制电路在从所述I / O焊盘发生到所述接地导轨的ESD事件期间向所述第一栅极提供接地电位。

公开(公告)号：US08724272B2

公开(公告)日：2014-05-13

申请号：US13454340

申请日：2012-04-24

申请人： Ying-Chang Lin ,  Da-Wei Lai

发明人： Ying-Chang Lin ,  Da-Wei Lai

IPC分类号： H02H3/22

CPC分类号： H01L27/0262 ,  H02H9/04

摘要： An ESD protection device with a tunable holding voltage is disclosed. Embodiments include: providing a silicon-controlled rectifier (SCR) having a first n-type layer with a cathode connection, a first p-type layer with a first control connection, a second n-type layer with a second control connection, and a second p-type layer with an anode connection; coupling the anode connection to a power rail; coupling the cathode connection to a ground rail; providing a tunable holding voltage control unit including a first NMOS having a first gate, a first drain, and a first source, wherein during an ESD event, the first NMOS is turned off and a holding voltage of the SCR is low; coupling the first drain to the first control connection; coupling the first source to the ground rail; and coupling the first gate to a program circuit.

摘要翻译： 公开了具有可调保持电压的ESD保护装置。 实施例包括：提供具有阴极连接的第一n型层的硅可控整流器（SCR），具有第一控制连接的第一p型层，具有第二控制连接的第二n型层，以及 具有阳极连接的第二p型层; 将阳极连接件连接到电源轨; 将阴极连接件连接到地面导轨上; 提供可调保持电压控制单元，其包括具有第一栅极，第一漏极和第一源极的第一NMOS，其中在ESD事件期间，第一NMOS截止，并且SCR的保持电压低; 将所述第一漏极耦合到所述第一控制连接; 将第一源耦合到地面导轨; 以及将所述第一栅极耦合到编程电路。

公开(公告)号：US20130279052A1

公开(公告)日：2013-10-24

申请号：US13454340

申请日：2012-04-24

申请人： Ying-Chang Lin ,  Da-Wei Lai

发明人： Ying-Chang Lin ,  Da-Wei Lai

IPC分类号： H02H9/04 ,  H05K3/10

CPC分类号： H01L27/0262 ,  H02H9/04

摘要： An ESD protection device with a tunable holding voltage is disclosed. Embodiments include: providing a silicon-controlled rectifier (SCR) having a first n-type layer with a cathode connection, a first p-type layer with a first control connection, a second n-type layer with a second control connection, and a second p-type layer with an anode connection; coupling the anode connection to a power rail; coupling the cathode connection to a ground rail; providing a tunable holding voltage control unit including a first NMOS having a first gate, a first drain, and a first source, wherein during an ESD event, the first NMOS is turned off and a holding voltage of the SCR is low; coupling the first drain to the first control connection; coupling the first source to the ground rail; and coupling the first gate to a program circuit.

摘要翻译： 公开了具有可调保持电压的ESD保护装置。 实施例包括：提供具有阴极连接的第一n型层的硅可控整流器（SCR），具有第一控制连接的第一p型层，具有第二控制连接的第二n型层，以及 具有阳极连接的第二p型层; 将阳极连接件连接到电源轨; 将阴极连接件连接到地面导轨上; 提供可调保持电压控制单元，其包括具有第一栅极，第一漏极和第一源极的第一NMOS，其中在ESD事件期间，第一NMOS截止，并且SCR的保持电压低; 将所述第一漏极耦合到所述第一控制连接; 将第一源耦合到地面导轨; 以及将所述第一栅极耦合到编程电路。

公开(公告)号：US20130235496A1

公开(公告)日：2013-09-12

申请号：US13415178

申请日：2012-03-08

申请人： Da-Wei Lai ,  Ying-Chang Lin ,  Mahadeva Iyer Natarajan

发明人： Da-Wei Lai ,  Ying-Chang Lin ,  Mahadeva Iyer Natarajan

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： An ESD-robust I/O driver circuit is disclosed. Embodiments include providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source to a ground rail and the first drain to an I/O pad; coupling a gate driver control circuit to the first drain and the first gate; and providing a ground potential to the first gate, via the gate driver control circuit, during an ESD event occurring from the I/O pad to the ground rail.

摘要翻译： 公开了一种ESD稳健的I / O驱动器电路。 实施例包括提供具有第一源极，第一漏极和第一栅极的第一NMOS晶体管; 将第一源耦合到接地导轨，将第一漏极耦合到I / O焊盘; 将栅极驱动器控制电路耦合到所述第一漏极和所述第一栅极; 以及在从I / O焊盘发生到地轨的ESD事件期间，经由栅极驱动器控制电路向第一栅极提供接地电位。

公开(公告)号：US09130010B2

公开(公告)日：2015-09-08

申请号：US13483322

申请日：2012-05-30

申请人： Da-Wei Lai

发明人： Da-Wei Lai

IPC分类号： H01L29/66 ,  H01L29/74 ,  H01L27/02 ,  H02H9/00

CPC分类号： H01L29/744 ,  H01L27/0262 ,  H01L27/0641 ,  H01L28/20 ,  H01L28/40 ,  H01L29/1012 ,  H01L29/7436

摘要： An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad.

摘要翻译： 公开了一种用于提供闭锁稳健的硅控制整流器（SCR）的方法。 实施例包括在用于SCR的衬底中提供第一N +区和第一P +区; 在靠近第一N +和P +区的衬底中提供第一和第二n-阱区; 在所述第一n阱区域中提供第二N +区域，以及在所述第二n阱区域中提供第二P +区域; 并且将第一N +和P +区域耦合到接地导轨，将第二N +区域耦合到电力轨道，将第二P +区域耦合到I / O焊盘。