公开(公告)号：US06362051B1

公开(公告)日：2002-03-26

申请号：US09648361

申请日：2000-08-25

Applicant: Jean Yang ,  Yider Wu ,  Hidehiko Shiraiwa ,  Mark Ramsbey

Inventor： Jean Yang ,  Yider Wu ,  Hidehiko Shiraiwa ,  Mark Ramsbey

IPC: H01L21336

CPC classification number: H01L21/28202 ,  H01L21/26533 ,  H01L21/28282 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518

Abstract: A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide at less than normal energy levels to reduce the amount of damage to the underlying semiconductor substrate. After low energy nitrogen implantation, the semiconductor structure is heated to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds is desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.

Abstract translation: 用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极 第二层氧化硅。 氮以低于正常能级注入到第一氧化硅层中以减少对下面的半导体衬底的损伤量。 在低能量氮注入之后，半导体结构被加热以退出注入损伤并将注入的氮扩散到衬底和氧化硅界面，以在该界面处形成SiN键。 SiN键是理想的，因为它们改善了界面处的结合强度，并且保留在氧化硅层中的氮增加了氧化物体的可靠性。

公开(公告)号：US06284600B1

公开(公告)日：2001-09-04

申请号：US09609468

申请日：2000-07-03

Applicant: Yider Wu ,  Mark T. Ramsbey ,  Chi Chang ,  Yu Sun ,  Tuan Duc Pham ,  Jean Y. Yang

Inventor： Yider Wu ,  Mark T. Ramsbey ,  Chi Chang ,  Yu Sun ,  Tuan Duc Pham ,  Jean Y. Yang

IPC: H01L21336

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A predetermined species such as nitrogen is placed at an interface between a bit line junction and a dielectric layer of a control dielectric structure of a flash memory device to minimize degradation of such an interface by minimizing formation of interface defects during program or erase operations of the flash memory device. The predetermined species such as nitrogen is implanted into a bit line junction of the flash memory device. A thermal process is performed that heats up the semiconductor wafer such that the predetermined species such as nitrogen implanted within the semiconductor wafer thermally drifts to the interface between the bit line junction and the control dielectric structure during the thermal process. The predetermined species such as nitrogen at the interface minimizes formation of interface defects and thus degradation of the interface with time during the program or erase operations of the flash memory device.

Abstract translation: 将诸如氮的预定物质放置在闪存存储器件的控制电介质结构的位线结和电介质层之间的界面处，以通过在编程或擦除操作期间最小化界面缺陷的形成来最小化这种界面的劣化 闪存设备。 将诸如氮的预定物质注入到闪速存储器件的位线结中。 执行加热半导体晶片的热处理，使得在热处理期间注入到半导体晶片内的预定物质例如氮漂移到位线结与控制电介质结构之间的界面。 在闪存器件的编程或擦除操作期间，预定种类例如接口处的氮使界面缺陷的形成最小化，从而使界面的时效性降低。

公开(公告)号：US20100227460A1

公开(公告)日：2010-09-09

申请号：US12399377

申请日：2009-03-06

Applicant: Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

Inventor： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

IPC: H01L21/4763

CPC classification number: H01L27/11521 ,  H01L21/76224

Abstract: In a method of manufacturing a NOR flash memory, when the memory device dimensions are further reduced, the forming of spacers at two lateral sides of the gate structures is omitted, and a space between two gate structures can be directly filled up with a dielectric spacer or a shallow trench isolation (STI) layer. Therefore, it is possible to avoid the problem of increased difficulty in manufacturing memory device caused by forming spacers in an extremely small space between the gate structures. The method also enables omission of the self-alignment step needed to form the salicide layer. Therefore, the difficulty in self-alignment due to the extremely small space between the gate structures can also be avoided.

Abstract translation: 在制造NOR闪速存储器的方法中，当存储器件尺寸进一步减小时，省略在栅极结构的两个侧面处形成间隔物，并且两个栅极结构之间的间隔可以直接用介电间隔件 或浅沟槽隔离（STI）层。 因此，可以避免在栅极结构之间的极小空间中形成间隔物而造成存储器件制造难度增大的问题。 该方法还能够省略形成硅化物层所需的自对准步骤。 因此，也可以避免由于栅极结构之间的极小空间而导致的自对准难度。

公开(公告)号：US20100099262A1

公开(公告)日：2010-04-22

申请号：US12254022

申请日：2008-10-20

Applicant: Yi-Hsiu Chen ,  Yung-Chung Lee ,  Yider Wu

Inventor： Yi-Hsiu Chen ,  Yung-Chung Lee ,  Yider Wu

IPC: H01L21/3105

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  Y10S438/976

Abstract: In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.

Abstract translation: 在制造非易失性存储单元的方法中，使用自对准金属硅化物代替常规钨金属层以形成多晶硅栅极，并且自对准金属硅化物用作多晶硅上的连接层 门。 通过使用自对准的金属硅化物来形成多晶硅栅极，可以节省在蚀刻工艺中使用掩模，从而能够简化制造工艺，从而降低制造成本。 同时，可以避免由氧化的钨金属层引起的电阻偏移的问题。

公开(公告)号：US07529132B2

公开(公告)日：2009-05-05

申请号：US11762369

申请日：2007-06-13

Applicant: Chao Yang Chen ,  Yider Wu ,  Hsiao Hua Lu

Inventor： Chao Yang Chen ,  Yider Wu ,  Hsiao Hua Lu

IPC: G11C11/34

CPC classification number: G11C16/0433

Abstract: A single-poly non-volatile memory includes a storing node, a control node and a floating gate. While a programming operation is executed, a bit line is provided with a low voltage and a control line is provided with a high voltage so that a coupling voltage occurs in the floating gate. The voltage difference between the floating gate and the storing node is able to send electrons into the floating gate, but the voltage difference between the floating gate and the control node is not enough to expel electrons from the floating gate. While an erasing operation is executed, a bit line is provided with a high voltage and a control line is provided with a low voltage so that a coupling voltage occurs on the floating gate. The voltage difference between the floating gate and the storing node is able to expel electrons from the floating gate, but the voltage difference between the floating gate and the control node is not enough to send electrons into the floating gate.

Abstract translation: 单聚多边形非易失性存储器包括存储节点，控制节点和浮动门。 当执行编程操作时，位线被提供有低电压，并且控制线被提供有高电压，使得在浮动栅极中发生耦合电压。 浮动栅极和存储节点之间的电压差能够将电子发送到浮动栅极，但是浮动栅极和控制节点之间的电压差不足以从浮动栅极排出电子。 当执行擦除操作时，位线被提供有高电压，并且控制线设置有低电压，使得在浮动栅极上发生耦合电压。 浮栅和存储节点之间的电压差能够从浮置栅极排出电子，但是浮栅和控制节点之间的电压差不足以将电子发送到浮置栅极。

公开(公告)号：US20090086548A1

公开(公告)日：2009-04-02

申请号：US11866018

申请日：2007-10-02

Applicant: Yider Wu ,  Yung-Chung Lee

Inventor： Yider Wu ,  Yung-Chung Lee

IPC: G11C11/34

CPC classification number: G11C16/0475

Abstract: A flash memory applied in NAND and/or NOR flash memory has a silicon-oxide-nitride-oxide-silicon cell structure, uses channel-hot-electron injection as a write mechanism thereof to have a localized trapping characteristic, and uses hot-hole injection as an erase mechanism thereof. The flash memory uses an oxide-nitride-oxide structure to replace a floating gate, and thereby solves the problem of an entire leakage caused by a local leakage of the floating gate. The flash memory may be miniaturized without the problem of data mutual interference, and may be easily integrated into the CMOS process to largely reduce the manufacturing cost thereof. Meanwhile, the flash memory also enables faster program time and erase time.

Abstract translation: 应用于NAND和/或NOR闪速存储器的闪速存储器具有氧化硅 - 氮化物 - 氧化物 - 硅电池结构，其通道 - 热电子注入作为其写入机制具有局部捕获特性，并且使用热孔 注射作为其擦除机制。 闪速存储器使用氧化物 - 氮化物 - 氧化物结构来代替浮动栅极，从而解决了浮栅的局部泄漏引起的整个泄漏的问题。 闪存可以小型化而没有数据相互干扰的问题，并且可以容易地集成到CMOS工艺中以大大降低其制造成本。 同时，闪存还可以实现更快的编程时间和擦除时间。

公开(公告)号：US20080079059A1

公开(公告)日：2008-04-03

申请号：US11789471

申请日：2007-04-20

Applicant: Yider Wu

Inventor： Yider Wu

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells. The select gate is formed with a STI recess process in advance locally in the select area.

Abstract translation: 旨在防止由浮动栅极之间的电荷的移动引起的数据破坏，从而提高可靠性的非易失性半导体存储器件包括埋入硅衬底中以隔离条形元件形成区域的元件隔离/绝缘膜。 经由第一栅极绝缘膜形成在衬底区域浮动栅极上，并且还经由第二栅极绝缘膜形成控制栅极。 源极和漏极扩散层与控制栅极自对准地形成。 浮动栅极上的第二栅极绝缘膜通过在元件隔离/绝缘膜上方的狭缝与浮动栅极分开并分离成各个存储单元的离散部分。 选择门在选择区域中局部地预先形成有STI凹陷处理。

公开(公告)号：US20070259493A1

公开(公告)日：2007-11-08

申请号：US11745059

申请日：2007-05-07

Applicant: KENT KUOHUA CHANG ,  Jongoh Kim ,  Yider Wu

Inventor： KENT KUOHUA CHANG ,  Jongoh Kim ,  Yider Wu

IPC: H01L21/8234

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

Abstract: A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.

Abstract translation: 描述了一种制造存储器件的方法。 在形成存储单元区域和半导体器件的外围区域的过程中，在形成在栅极的侧壁上的间隔物之前，在存储单元区域上形成光致抗蚀剂层。 因此，在外围电路区域中形成间隔物的过程中，防止存储单元区域被损坏以减轻漏电流问题。

公开(公告)号：US20050121716A1

公开(公告)日：2005-06-09

申请号：US10726508

申请日：2003-12-04

Applicant: Wiley Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

Inventor： Wiley Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

IPC: G11C16/04 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/785

Abstract: A memory device includes a conductive structure, a number of dielectric layers and a control gate. The dielectric layers are formed around the conductive structure and the control gate is formed over the dielectric layers. A portion of the conductive structure functions as a drain region for the memory device and at least one of the dielectric layers functions as a charge storage structure for the memory device. The dielectric layers may include oxide-nitride-oxide layers.

Abstract translation: 存储器件包括导电结构，多个电介质层和控制栅极。 电介质层形成在导电结构周围，并且控制栅极形成在电介质层上。 导电结构的一部分用作存储器件的漏极区，并且至少一个介电层用作存储器件的电荷存储结构。 电介质层可以包括氧化物 - 氮化物 - 氧化物层。

公开(公告)号：US06737701B1

公开(公告)日：2004-05-18

申请号：US10313454

申请日：2002-12-05

Applicant: Amy C. Tu ,  Jean Yee-Mei Yang ,  Yider Wu

Inventor： Amy C. Tu ,  Jean Yee-Mei Yang ,  Yider Wu

IPC: H01L31119

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: According to one exemplary embodiment, a structure comprises a first bit line and a second bit line. The structure further comprises a first memory cell situated over the first bit line, where the first memory cell comprises a first ONO stack segment, and where the first ONO stack segment is situated between the first bit line and a word line. The structure further comprises a second memory cell situated over the second bit line, where the second memory cell comprises a second ONO stack segment, where the second ONO stack segment is situated between the second bit line and the word line, and where the first ONO stack segment is separated from the second ONO stack segment by a gap. The first memory cell and the second memory cell may each be capable, for example, of storing two independent data bits.

Abstract translation: 根据一个示例性实施例，一种结构包括第一位线和第二位线。 该结构还包括位于第一位线之上的第一存储器单元，其中第一存储器单元包括第一ONO堆栈段，并且其中第一ONO堆栈段位于第一位线和字线之间。 该结构还包括位于第二位线之上的第二存储器单元，其中第二存储器单元包括第二ONO堆栈段，其中第二ONO堆栈段位于第二位线和字线之间，并且其中第一ONO 堆叠段与第二ONO堆栈段间隔开。 第一存储器单元和第二存储单元可以各自能够例如存储两个独立的数据位。