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    Method of forming ONO flash memory devices using rapid thermal oxidation
    1.
    发明授权
    Method of forming ONO flash memory devices using rapid thermal oxidation 有权
    使用快速热氧化形成ONO闪存器件的方法

    公开(公告)号：US06395654B1

    公开(公告)日：2002-05-28

    申请号：US09648077

    申请日：2000-08-25

    申请人： Jean Yang ,  Yider Wu ,  Hidehiko Shiraiwa ,  Mark Ramsbey

    发明人： Jean Yang ,  Yider Wu ,  Hidehiko Shiraiwa ,  Mark Ramsbey

    IPC分类号： H01L21225

    CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

    摘要： A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide and then the semiconductor structure is heated using a rapid thermal tool to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds are desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.

    摘要翻译： 用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极 第二层氧化硅。 将氮注入到第一层氧化硅中，然后使用快速热工具来加热半导体结构，以退出植入物损伤并将植入的氮扩散到衬底和氧化硅界面，以在该位置形成SiN键 接口。 SiN键是期望的，因为它们改善了界面处的结合强度，并且保留在氧化硅层中的氮增加了氧化物体的可靠性。

    Method of forming ONO flash memory devices using low energy nitrogen implantation
    2.
    发明授权
    Method of forming ONO flash memory devices using low energy nitrogen implantation 有权
    使用低能氮注入形成ONO闪存器件的方法

    公开(公告)号：US06362051B1

    公开(公告)日：2002-03-26

    申请号：US09648361

    申请日：2000-08-25

    申请人： Jean Yang ,  Yider Wu ,  Hidehiko Shiraiwa ,  Mark Ramsbey

    发明人： Jean Yang ,  Yider Wu ,  Hidehiko Shiraiwa ,  Mark Ramsbey

    IPC分类号： H01L21336

    CPC分类号： H01L21/28202 ,  H01L21/26533 ,  H01L21/28282 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518

    摘要： A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide at less than normal energy levels to reduce the amount of damage to the underlying semiconductor substrate. After low energy nitrogen implantation, the semiconductor structure is heated to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds is desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.

    摘要翻译： 用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极 第二层氧化硅。 氮以低于正常能级注入到第一氧化硅层中以减少对下面的半导体衬底的损伤量。 在低能量氮注入之后，半导体结构被加热以退出注入损伤并将注入的氮扩散到衬底和氧化硅界面，以在该界面处形成SiN键。 SiN键是理想的，因为它们改善了界面处的结合强度，并且保留在氧化硅层中的氮增加了氧化物体的可靠性。

    Nitrogen implant after bit-line formation for ONO flash memory devices
    4.
    发明授权
    Nitrogen implant after bit-line formation for ONO flash memory devices 有权
    ONO闪存器件位线形成后的氮注入

    公开(公告)号：US06403420B1

    公开(公告)日：2002-06-11

    申请号：US09627664

    申请日：2000-07-28

    申请人： Jean Yang ,  Yider Wu ,  Mark Ramsbey ,  Yu Sun

    发明人： Jean Yang ,  Yider Wu ,  Mark Ramsbey ,  Yu Sun

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L21/26506 ,  H01L21/28282 ,  H01L21/76202 ,  H01L27/115 ,  H01L29/66833

    摘要： A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted after the ONO layer and junction areas have been formed. The entire semiconductor structure is heated to anneal out the nitrogen implant damage and to diffuse or drive the implanted nitrogen into the substrate and silicon oxide interface to form strong SiN bonds at that interface. By implanting nitrogen into the ONO stack, instead of a single silicon oxide layer as done conventionally, damage to the underlying silicon substrate is reduced. This results in better isolation between adjacent bit lines and suppresses leakages between adjacent bit lines.

    摘要翻译： 用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极 第二层氧化硅。 在ONO层和接合区域已经形成之后注入氮。 整个半导体结构被加热以退出氮注入损伤，并将注入的氮扩散或驱动到衬底和氧化硅界面中，以在该界面处形成强的SiN键。 通过将氮气注入到ONO堆叠中，代替如常规制造的单个氧化硅层，降低了底层硅衬底的损坏。 这导致相邻位线之间更好的隔离并且抑制相邻位线之间的泄漏。

    Dummy wordline for erase and bitline leakage
    5.
    发明授权
    Dummy wordline for erase and bitline leakage 有权
    用于擦除和位线泄漏的虚拟字线

    公开(公告)号：US06707078B1

    公开(公告)日：2004-03-16

    申请号：US10230729

    申请日：2002-08-29

    申请人： Hidehiko Shiraiwa ,  Yider Wu ,  Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Darlene G. Hamilton

    发明人： Hidehiko Shiraiwa ,  Yider Wu ,  Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Darlene G. Hamilton

    IPC分类号： H01L2968

    CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L27/115

    摘要： One aspect of the present invention relates to a SONOS type non-volatile semiconductor memory device having improved erase speed, the device containing bitlines extending in a first direction; wordlines extending in a second direction, the wordlines comprising functioning wordlines and at least one dummy wordline, wherein the dummy wordline is positioned near at least one of a bitline contact and an edge of the core region, and the dummy wordline is treated so as not to cycle between on and off states. Another aspect of the present invention relates to a method of making a SONOS type non-volatile semiconductor memory device having improved erase speed, involving forming a plurality of bitlines extending in a first direction in the core region; forming a plurality of functioning wordlines extending in a second direction in the core region; forming at least one dummy wordline between the functioning wordlines and the periphery region or between the functioning wordlines and a bitline contact and treating the device so that the dummy wordline does not cycle between on and off states.

    摘要翻译： 本发明的一个方面涉及一种具有改进的擦除速度的SONOS型非易失性半导体存储器件，该器件含有沿第一方向延伸的位线; 所述字线在第二方向上延伸，所述字线包括功能字线和至少一个伪字线，其中所述伪字线位于所述芯区域的位线接触和边缘中的至少一个附近，并且所述伪字线被处理为不 在开关状态之间循环。 本发明的另一方面涉及一种制造具有改进的擦除速度的SONOS型非易失性半导体存储器件的方法，包括形成在芯区域中沿第一方向延伸的多个位线; 形成在所述芯区域中沿第二方向延伸的多个功能字线; 在功能字线和外围区域之间或在功能字线和位线接触之间形成至少一个伪字线，并对器件进行处理，使得伪字线不会在导通和关断状态之间循环。

    Method of simultaneous formation of bitline isolation and periphery oxide
    6.
    发明授权
    Method of simultaneous formation of bitline isolation and periphery oxide 有权
    同时形成位线隔离和周边氧化物的方法

    公开(公告)号：US06468865B1

    公开(公告)日：2002-10-22

    申请号：US09723653

    申请日：2000-11-28

    申请人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

    发明人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; forming a bitline isolation over the buried bitlines in the core region; and forming gates in the core region and the periphery region. Another aspect of the present invention relates to increasing the thickness of the gate dielectric in at least a portion of the periphery region simultaneously while forming the bitline isolation.

    摘要翻译： 本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 去除位于芯区域中的掩埋位线之上的电荷捕获电介质的至少一部分; 在核心区域的掩埋位线上形成位线隔离; 并且在芯区域和周边区域中形成栅极。 本发明的另一方面涉及在形成位线隔离的同时在周边区域的至少一部分中增加栅极电介质的厚度。

    Flash memory erase speed by fluorine implant or fluorination
    7.
    发明授权
    Flash memory erase speed by fluorine implant or fluorination 失效
    闪存擦除速度由氟注入或氟化

    公开(公告)号：US06445030B1

    公开(公告)日：2002-09-03

    申请号：US09772600

    申请日：2001-01-30

    申请人： Yider Wu ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Che-Hoo Ng

    发明人： Yider Wu ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Che-Hoo Ng

    IPC分类号： H01L2972

    CPC分类号： H01L21/28211 ,  H01L21/28282 ,  H01L29/511 ,  H01L29/792

    摘要： One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a silicon substrate; a tunnel oxide layer over the silicon substrate, the tunnel oxide layer comprising fluorine atoms; a charge trapping layer over the tunnel oxide layer; an electrode or poly layer over the charge trapping layer; and source and drain regions within the silicon substrate. Another aspect of the present invention relates to a method of making a non-volatile semiconductor memory cell having improved erase speed, involving the steps of providing a silicon substrate; forming a tunnel oxide layer comprising fluorine atoms over the silicon substrate; and forming non-volatile memory cells over the tunnel oxide layer.

    摘要翻译： 本发明的一个方面涉及一种包含硅衬底的非易失性半导体存储器件; 硅衬底上的隧道氧化物层，所述隧道氧化物层包含氟原子; 在隧道氧化物层上方的电荷捕获层; 在电荷捕获层上方的电极或多晶硅层; 以及硅衬底内的源区和漏区。 本发明的另一方面涉及一种制造具有改善的擦除速度的非易失性半导体存储单元的方法，包括提供硅衬底的步骤; 在所述硅衬底上形成包含氟原子的隧道氧化物层; 以及在所述隧道氧化物层上形成非易失性存储单元。

    Hard mask process for memory device without bitline shorts
    8.
    发明授权
    Hard mask process for memory device without bitline shorts 有权
    内存设备的硬掩模处理，无位线短路

    公开(公告)号：US06706595B2

    公开(公告)日：2004-03-16

    申请号：US10100485

    申请日：2002-03-14

    申请人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Yider Wu ,  Emmanuil Lingunis ,  Tazrien Kamal

    发明人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Yider Wu ,  Emmanuil Lingunis ,  Tazrien Kamal

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. The hard mask is of a material formulated for removal without damaging the charge-trapping dielectric layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A salicide is grown without short-circuiting the first and second bitlines.

    摘要翻译： 用于MirrorBit（闪存）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质层。 植入第一和第二位线，并存放字线层。 硬掩模层沉积在字线层上。 硬掩模是配制用于去除而不损坏电荷捕获介电层的材料。 光刻胶沉积在字线层上并用于形成硬掩模。 去除光致抗蚀剂。 使用硬掩模处理字线层以形成字线，并且去除硬掩模。 生长自杀剂不会使第一和第二位线短路。