公开(公告)号：US20100208512A1

公开(公告)日：2010-08-19

申请号：US12709256

申请日：2010-02-19

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C11/00

CPC分类号： G11C17/12 ,  G11C13/0002 ,  G11C14/0081 ,  G11C14/009

摘要： A latch circuit is connected to a first common node, a first, second output node, and a first, second connection node. A first resistance change element is connected to the first connection node, and a second common node. A second resistance change element is connected to the second connection node, and the second common node. When a first data is stored, voltages of the first common node, second common node, and first output node are set at a first reference voltage, and a voltage of the second output node is set at a second reference voltage. When a second data is stored, voltages of the first common node, second common node, and second output node are set at the first reference voltage, and a voltage of the first output node is set at the second reference voltage.

摘要翻译： 锁存电路连接到第一公共节点，第一，第二输出节点和第一，第二连接节点。 第一电阻变化元件连接到第一连接节点和第二公共节点。 第二电阻变化元件连接到第二连接节点和第二公共节点。 当存储第一数据时，将第一公共节点，第二公共节点和第一输出节点的电压设置为第一参考电压，并将第二输出节点的电压设置为第二参考电压。 当存储第二数据时，将第一公共节点，第二公共节点和第二输出节点的电压设置为第一参考电压，并且将第一输出节点的电压设置为第二参考电压。

公开(公告)号：US20090010045A1

公开(公告)日：2009-01-08

申请号：US12164410

申请日：2008-06-30

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C11/02

CPC分类号： G11C11/15 ,  G11C11/1673

摘要： A MRAM includes a first magnetoresistive effect (MR) element that takes a low and high resistance states. A second MR element is fixed to a low or high resistance state. First and second MOSFETs are connected to the first and second MR elements, respectively. A sense amplifier amplifies a difference between values of current flowing through the first and second MOSFETs. A current circuit outputs reference current whose value lies between current flowing through the first MR element of the low and high resistance states. A third MOSFET has one end that receives the reference current and is connected to its own gate terminal. The gate terminal of the second MOSFET receives the same potential as the gate terminal of the third MOSFET. A first resistance element is connected to the others end of the third MOSFET and has the same resistance as the second magnetoresistive effect element.

摘要翻译： MRAM包括采用低和高电阻状态的第一磁阻效应（MR）元件。 第二MR元件固定为低电阻或高电阻状态。 第一和第二MOSFET分别连接到第一和第二MR元件。 读出放大器放大流经第一和第二MOSFET的电流值之差。 电流电路输出其值位于流过低电阻状态和高电阻状态的第一MR元件的电流之间的参考电流。 第三个MOSFET的一端接收参考电流并连接到其自己的栅极端子。 第二MOSFET的栅极端子接收与第三MOSFET的栅极端子相同的电位。 第一电阻元件连接到第三MOSFET的另一端，并且具有与第二磁阻效应元件相同的电阻。

公开(公告)号：US20080043514A1

公开(公告)日：2008-02-21

申请号：US11781443

申请日：2007-07-23

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C11/00

CPC分类号： G11C7/02 ,  G11C7/18 ,  G11C11/1675 ,  G11C13/0004

摘要： A semiconductor memory according to examples of the present invention includes a word line extending in a first direction, first, second and third bit lines extending in a second direction, a first cell unit connected between the first and second bit lines, a second cell unit connected between the first and third bit lines, and a controller CNT which executes write to a first resistance change element under the condition that the word line is made active and potentials of the first and third bit lines are equalized, and which executes write to a second resistance change element under the condition that the word line is made active and potentials of the first and second bit lines are equalized.

摘要翻译： 根据本发明的示例的半导体存储器包括在第一方向上延伸的字线，在第二方向上延伸的第一，第二和第三位线，连接在第一和第二位线之间的第一单元单元，第二单元单元 连接在第一和第三位线之间的控制器CNT，以及在使字线有效并且第一和第三位线的电位相等的条件下执行写入第一电阻变化元件的控制器CNT，并且执行写入到 第二电阻变化元件在使字线有效并且第一和第二位线的电位相等的条件下。

公开(公告)号：US20120069629A1

公开(公告)日：2012-03-22

申请号：US13234587

申请日：2011-09-16

申请人： Yoshihiro UEDA ,  Akira KATAYAMA ,  Ryousuke TAKIZAWA

发明人： Yoshihiro UEDA ,  Akira KATAYAMA ,  Ryousuke TAKIZAWA

IPC分类号： G11C11/00 ,  G11C7/06 ,  G11C17/16

CPC分类号： G11C13/0023 ,  G11C7/065 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C17/143 ,  G11C2013/0054

摘要： According to one embodiment, a semiconductor memory device includes a first reference cell being arranged in a first cell array, and a plurality of first fuse cells being arranged in the first cell array. The first reference cell and the plurality of first fuse cells are arranged on the same row or column.

摘要翻译： 根据一个实施例，半导体存储器件包括布置在第一单元阵列中的第一参考单元，以及布置在第一单元阵列中的多个第一熔丝单元。 第一参考单元和多个第一保险丝单元布置在同一行或列上。

公开(公告)号：US20100277972A1

公开(公告)日：2010-11-04

申请号：US12769523

申请日：2010-04-28

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C11/00 ,  G11C7/06

CPC分类号： G11C11/1673 ,  G11C11/1659

摘要： First and second memory cell arrays are adjacent in a first direction. First and second areas are positioned adjacent to one and the other side of the first memory array in a second direction. Third and fourth areas are positioned adjacent to one and the other side of the second memory array in a second direction. A sense amplifier is arranged in the first area and a current sink is arranged in the fourth area. The sense amplifier compares a read current which flows into the current sink via a memory cell in the first memory cell array and the second area from the sense amplifier with a reference current which flows into the current sink via the third area and a reference memory cell in the second memory cell array from the sense amplifier.

摘要翻译： 第一和第二存储单元阵列在第一方向上相邻。 第一和第二区域在第二方向上与第一存储器阵列的一侧和另一侧相邻。 第三和第四区域在第二方向上与第二存储器阵列的一侧和另一侧相邻。 读出放大器布置在第一区域中，并且电流吸收器布置在第四区域中。 读出放大器经由第一存储单元阵列中的存储单元和来自读出放大器的第二区域经由第三区域和参考存储单元比较流入电流宿中的参考电流来流入流入电流宿的读取电流， 在来自读出放大器的第二存储单元阵列中。

公开(公告)号：US20080283946A1

公开(公告)日：2008-11-20

申请号：US12119720

申请日：2008-05-13

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： G11C11/16 ,  B82Y10/00 ,  H01L27/228

摘要： A magnetic random access memory includes a transistor having a gate electrode formed above a surface of a substrate, and first and second impurity diffusion regions which sandwich a channel region below the gate electrode, a first plug formed on the first impurity diffusion region, a recording element formed on the first plug, including a plurality of stacked layers, and configured to hold information in accordance with an internal magnetization state, a first signal line formed on the recording element, a second plug formed on the second impurity diffusion region, an electrical conductor formed on the second plug, an area of a shape of the electrical conductor, which is projected onto the surface of the substrate, being larger than that of a shape of the recording element, which is projected onto the surface of the substrate, and a second signal line formed on the electrical conductor.

摘要翻译： 磁性随机存取存储器包括晶体管，其具有形成在衬底表面上的栅电极，以及夹在栅电极下方的沟道区的第一和第二杂质扩散区，形成在第一杂质扩散区上的第一插塞， 元件，形成在第一插头上，包括多个堆叠层，并且被配置为根据内部磁化状态保存信息，形成在记录元件上的第一信号线，形成在第二杂质扩散区上的第二插塞，电 导体形成在第二插头上，突出到基板的表面上的电导体的形状的面积大于投影到基板的表面上的记录元件的形状， 形成在电导体上的第二信号线。

公开(公告)号：US20070268733A1

公开(公告)日：2007-11-22

申请号：US11736300

申请日：2007-04-17

申请人： Yoshihiro UEDA ,  Tsuneo INABA

发明人： Yoshihiro UEDA ,  Tsuneo INABA

IPC分类号： G11C5/06

CPC分类号： G11C11/16

摘要： A magnetic storage device includes magnetoresistance effect elements. First and second write lines extend along a first direction. Current flows in the first and second write lines only in the first direction and a second direction opposite to the first direction, respectively. A third write line extends along a third direction orthogonal to the first direction. The elements are respectively placed where the first and third write lines cross and the second and third write lines cross. First and second electrodes are provided between the first and third write lines and between the second and third write lines. First and second plugs are respectively connected to the first and second electrodes. The first plug stands at a position apart from the first write line along the third direction. The second plug stands at a position apart from the second write line along the opposite direction to the third direction.

摘要翻译： 磁存储装置包括磁阻效应元件。 第一和第二写入线沿着第一方向延伸。 电流仅在第一方向和与第一方向相反的第二方向上分别在第一和第二写入线中流动。 第三写入线沿着与第一方向正交的第三方向延伸。 元件分别放置在第一和第三写入线交叉的位置，第二和第三写入线交叉。 第一和第二电极设置在第一和第三写入线之间以及第二和第三写入线之间。 第一和第二插头分别连接到第一和第二电极。 第一插头位于沿着第三方向与第一写入线分开的位置处。 第二插头沿着与第三方向相反的方向站立在与第二写入线分开的位置处。

公开(公告)号：US20070258282A1

公开(公告)日：2007-11-08

申请号：US11682934

申请日：2007-03-07

申请人： Yoshihiro UEDA ,  Tsuneo Inaba ,  Yuui Shimizu ,  Kiyotaro Itagaki

发明人： Yoshihiro UEDA ,  Tsuneo Inaba ,  Yuui Shimizu ,  Kiyotaro Itagaki

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： A magnetic memory device includes a magnetoresistance element which has first and second ends. First data is written into the magnetoresistance element by an electric current flowing from the first end to the second end. Second data is written into the magnetoresistance element by an electric current flowing from the second end to the first end. A first p-type MOSFET has one end connected to the first end. A second p-type MOSFET has one end connected to the second end. A first n-type MOSFET has one end connected to the first end. A second n-type MOSFET has one end connected to the second end. A current source circuit is connected to each another end of the first and second p-type MOSFETs and supplies an electric current. A current sink circuit is connected to each another end of the first and second n-type MOSFETs and draws an electric current.

摘要翻译： 磁存储器件包括具有第一和第二端的磁阻元件。 第一数据通过从第一端流到第二端的电流写入磁阻元件。 通过从第二端流到第一端的电流将第二数据写入磁阻元件。 第一p型MOSFET的一端连接到第一端。 第二p型MOSFET的一端连接到第二端。 第一n型MOSFET的一端连接到第一端。 第二个n型MOSFET的一端连接到第二端。 电流源电路连接到第一和第二p型MOSFET的另一端并提供电流。 电流吸收电路连接到第一和第二n型MOSFET的另一端，并且吸收电流。

公开(公告)号：US20130250653A1

公开(公告)日：2013-09-26

申请号：US13601492

申请日：2012-08-31

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C11/21 ,  G11C11/02 ,  G11C7/06

CPC分类号： G11C11/16 ,  G11C11/1673 ,  G11C11/1693

摘要： A memory includes storage elements, a signal holding part and a sense amplifier. A driving-method includes a read operation for reading target data stored in a first storage element of the storage elements. In the read operation, the signal holding part holds a first voltage according to the target data. First sample data of a first logic is written to the first storage element. The signal holding part holds a second voltage according to the first sample data. Second sample data of a second logic opposite to the first logic is written to the first storage element. The signal holding part holds a third voltage according to the second sample data. The sense amplifier compares a read signal based on the first voltage with a reference signal generated based on the second and third voltages to detect a logic of the target data stored in the first storage element.

摘要翻译： 存储器包括存储元件，信号保持部分和读出放大器。 驱动方法包括用于读取存储在存储元件的第一存储元件中的目标数据的读取操作。 在读取操作中，信号保持部分根据目标数据保持第一电压。 将第一逻辑的第一样本数据写入第一存储元件。 信号保持部根据第一采样数据保持第二电压。 与第一逻辑相反的第二逻辑的第二采样数据被写入第一存储元件。 信号保持部根据第二采样数据保持第三电压。 感测放大器将基于第一电压的读取信号与基于第二和第三电压产生的参考信号进行比较，以检测存储在第一存储元件中的目标数据的逻辑。

公开(公告)号：US20070297210A1

公开(公告)日：2007-12-27

申请号：US11736379

申请日：2007-04-17

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C17/00

CPC分类号： G11C16/10

摘要： A semiconductor memory device includes a power supply circuit which generates a write current, a write line to which a logic state is transferred, a first pass transistor connected between the power supply circuit and the write line, and a first register which connects to the write line, receives a logic state of the write line in an input state, stores the received logic state in a storage state, and controls an on/off state of the first pass transistor on the basis of the stored logic state.

摘要翻译： 半导体存储器件包括产生写入电流的电源电路，连接在电源电路和写入线之间的连接在其上的第一通过晶体管和逻辑状态被传送到的写入线，以及连接到写入的第一寄存器 在输入状态下接收写入线的逻辑状态，将接收到的逻辑状态存储在存储状态，并且基于所存储的逻辑状态来控制第一遍晶体管的导通/截止状态。