Semiconductor device including first and second sidewalls and method of manufacturing semiconductor device
    12.
    发明授权
    Semiconductor device including first and second sidewalls and method of manufacturing semiconductor device 有权
    包括第一和第二侧壁的半导体器件和制造半导体器件的方法

    公开(公告)号:US07842576B2

    公开(公告)日:2010-11-30

    申请号:US12588931

    申请日:2009-11-03

    申请人: Yoshitaka Kubota

    发明人: Yoshitaka Kubota

    IPC分类号: H01L21/336

    摘要: The invention provides a method of manufacturing a semiconductor device including a non-volatile memory with high yield, and a semiconductor device manufactured by the method. A method of manufacturing a semiconductor device includes a process of forming a second side wall such that the width of the second side wall, which is formed on the side of a portion of a second gate electrode that does not face dummy gates on a drain forming region side, in a gate length direction is larger than that of the second side wall, which is formed on the side of the second gate electrode on a source forming region side, in the gate length direction, in a non-volatile memory forming region.

    摘要翻译: 本发明提供了一种制造包括具有高产率的非易失性存储器的半导体器件的方法以及通过该方法制造的半导体器件。 一种制造半导体器件的方法包括形成第二侧壁的工艺,使得形成在第二栅电极的不在漏极形成上的虚拟栅极的一侧的一侧上的第二侧壁的宽度 在栅极长度方向上的栅极长度方向的栅极长度方向上的栅极长度方向上的栅极长度方向上的栅极长度方向上的栅极长度方向上的栅极长度方向上的栅极长度方向上, 。

    Electrical fuse, semiconductor device and method of disconnecting electrical fuse
    13.
    发明申请
    Electrical fuse, semiconductor device and method of disconnecting electrical fuse 失效
    电气保险丝,半导体装置及断开电气保险丝的方法

    公开(公告)号:US20090231020A1

    公开(公告)日:2009-09-17

    申请号:US12453053

    申请日:2009-04-28

    申请人: Yoshitaka Kubota

    发明人: Yoshitaka Kubota

    IPC分类号: H01H85/00 H01L23/525

    摘要: An electrical fuse including a polysilicon layer; a silicide layer formed over the polysilicon layer; and a first metal contact and a second metal contact arranged over the silicide layer, while being spaced from each other, the electrical fuse being configured so that the silicide layer, after disconnection, is excluded from a region right under the second metal contact, and from a region between the second metal contact and the first metal contact is provided.

    摘要翻译: 包括多晶硅层的电熔丝; 形成在所述多晶硅层上的硅化物层; 以及设置在所述硅化物层上方的第一金属触点和第二金属触点,并且彼此间隔开,所述电熔丝被构造成使得所述硅化物层在断开之后被排除在所述第二金属触点正下方的区域中,以及 提供从第二金属触点和第一金属触点之间的区域。

    Vapor deposition material
    14.
    发明授权
    Vapor deposition material 失效
    气相沉积材料

    公开(公告)号:US5789330A

    公开(公告)日:1998-08-04

    申请号:US874341

    申请日:1997-06-13

    摘要: A vapor deposition material which is a sintered body of zirconia containing a stabilizer, wherein the content of monoclinic phase is from 25 to 70%, the content of tetragonal phase is at most 3% and the rest is cubic phase, and of which the bulk density is from 3.0 to 5.0 g/cm.sup.3, the porosity is from 15 to 50%, the mode size of pores is from 0.5 to 3 .mu.m, and the volume of pores of from 0.1 to 5 .mu.m constitutes at least 90% of the total pore volume.

    摘要翻译: 作为含有稳定剂的氧化锆烧结体的气相沉积材料,其中单斜相含量为25〜70%,四方相为3%以下,其余为立方相,其中体积 密度为3.0〜5.0g / cm 3,孔隙率为15〜50%,孔的模尺寸为0.5〜3μm,孔的体积为0.1〜5μm构成至少90% 总孔体积。

    Elastomer-coated cloth composite
    16.
    发明授权
    Elastomer-coated cloth composite 失效
    弹性体涂层布复合材料

    公开(公告)号:US4530868A

    公开(公告)日:1985-07-23

    申请号:US561603

    申请日:1983-12-14

    摘要: This invention describes a water-impermeable elastomer-coated cloth composite in which the end sections of mutually adjacent elastomer-coated cloths are overlapped and sewn together in such a way that the thread passes up and down through this overlapped section. After a seam is sewn together, it is covered by an adhesive tape applied so that it extends over the sewn section of the seam and onto the portion of each section of the cloth beyond the sewn section to form a strong, watertight, airtight composite.

    摘要翻译: 本发明描述了一种不透水弹性体涂布布复合物,其中相互相邻的弹性体涂布布的端部重叠并缝合在一起,使得线穿过该重叠部分上下移动。 将缝缝合在一起后,用粘合带覆盖,使其在接缝的缝合部分上延伸到织物的每个部分的超过缝合部分的部分上以形成坚固的,防水的气密复合材料。

    Method of manufacturing semiconductor device and semiconductor device
    17.
    发明授权
    Method of manufacturing semiconductor device and semiconductor device 失效
    制造半导体器件和半导体器件的方法

    公开(公告)号:US08213209B2

    公开(公告)日:2012-07-03

    申请号:US12826100

    申请日:2010-06-29

    摘要: In a method of manufacturing a semiconductor device, element properties of an element property extraction pattern formed on a semiconductor wafer is extracted as element properties of a current control element corresponding to the element property extraction pattern. A supply energy to the current control element is set which is formed between nodes on the semiconductor wafer, based on the extracted element properties. The set supply energy is supplied to the current control element to irreversible control an electrical connection between the nodes through the device breakdown by the current control element.

    摘要翻译: 在制造半导体器件的方法中,提取形成在半导体晶片上的元素特性提取图案的元素性质作为与元素特性提取图案对应的电流控制元件的元素特性。 基于所提取的元件特性,设置在半导体晶片上的节点之间形成对电流控制元件的供给能量。 设定的供给能量被提供给电流控制元件,以通过由电流控制元件击穿的装置不可逆地控制节点之间的电连接。

    Electrical fuse, semiconductor device and method of disconnecting electrical fuse
    18.
    发明授权
    Electrical fuse, semiconductor device and method of disconnecting electrical fuse 失效
    电气保险丝,半导体装置及断开电气保险丝的方法

    公开(公告)号:US08178943B2

    公开(公告)日:2012-05-15

    申请号:US12453053

    申请日:2009-04-28

    申请人: Yoshitaka Kubota

    发明人: Yoshitaka Kubota

    IPC分类号: H01L23/52

    摘要: An electrical fuse including a polysilicon layer; a silicide layer formed over the polysilicon layer; and a first metal contact and a second metal contact arranged over the silicide layer, while being spaced from each other, the electrical fuse being configured so that the silicide layer, after disconnection, is excluded from a region right under the second metal contact, and from a region between the second metal contact and the first metal contact is provided.

    摘要翻译: 包括多晶硅层的电熔丝; 形成在所述多晶硅层上的硅化物层; 以及设置在所述硅化物层上方的第一金属触点和第二金属触点,并且彼此间隔开,所述电熔丝被构造成使得所述硅化物层在断开之后被排除在所述第二金属触点正下方的区域中,以及 提供从第二金属触点和第一金属触点之间的区域。

    Semiconductor device
    19.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号:US20100096724A1

    公开(公告)日:2010-04-22

    申请号:US12588223

    申请日:2009-10-08

    IPC分类号: H01L23/525

    摘要: A semiconductor device (200) includes an electric fuse (100) including: an upper layer fuse interconnect (112) formed on a substrate (not shown); a lower layer fuse interconnect (122); and a via (130) which is connected to one end of the upper layer fuse interconnect (112) and connects the upper layer fuse interconnect (112) and the lower layer fuse interconnect (122). The upper fuse interconnect (112) includes a width varying region (118) having a small interconnect width on a side of the one end.

    摘要翻译: 半导体器件(200)包括电熔丝(100),包括:形成在衬底(未示出)上的上层熔丝互连(112); 下层熔丝互连(122); 以及连接到上层熔丝互连(112)的一端并连接上层熔丝互连(112)和下层熔丝互连(122)的通孔(130)。 上部熔丝互连(112)包括在一端的一侧具有小互连宽度的宽度变化区(118)。