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公开(公告)号：US09111934B2
公开(公告)日：2015-08-18
申请号：US13137032
申请日：2011-07-15
IPC分类号： H01L23/52 , H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.
摘要翻译： 半导体器件包括电熔丝和用于向电熔丝施加电压的第一和第二大面积布线。 电熔丝包括熔丝单元，其包括上层熔丝布线，下层熔丝布线和连接上层熔丝布线和下层熔丝布线的布线，上层引出布线 连接上层熔丝布线和第一大面积布线并具有弯曲图案，以及连接下层熔丝布线和第二大面积布线并具有弯曲图案的下层引出布线。
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公开(公告)号：US08942023B2
公开(公告)日：2015-01-27
申请号：US13566575
申请日：2012-08-03
CPC分类号： G11C7/24 , G06F21/75 , G06F21/79 , G11C13/0004 , G11C13/003 , G11C13/0059 , G11C17/16 , G11C2213/74 , G11C2213/79 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device using resistive random access memory (ReRAM) elements and having improved tamper resistance is provided. The semiconductor device is provided with a unit cell which stores one bit of cell data and a control circuit. The unit cell includes n ReRAM elements (n being an integer of 2 or larger). At least one of the ReRAM elements is an effective element where the cell data is recorded. In reading the cell data, the control circuit at least selects the effective element and reads data recorded thereon as the cell data.
摘要翻译： 提供了一种使用电阻随机存取存储器（ReRAM）元件并具有改进的防篡改性的半导体器件。 半导体器件设置有存储一位单元数据的单元单元和控制电路。 单位单元包括n个ReRAM元素（n是2或更大的整数）。 ReRAM元素中的至少一个是记录单元数据的有效元素。 在读取单元数据时，控制电路至少选择有效元件并将其上记录的数据读取为单元数据。
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公开(公告)号：US08080861B2
公开(公告)日：2011-12-20
申请号：US12588202
申请日：2009-10-07
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.
摘要翻译： 半导体器件包括电熔丝和用于向电熔丝施加电压的第一和第二大面积布线。 电熔丝包括熔丝单元，其包括上层熔丝布线，下层熔丝布线和连接上层熔丝布线和下层熔丝布线的布线，上层引出布线 连接上层熔丝布线和第一大面积布线并具有弯曲图案，以及连接下层熔丝布线和第二大面积布线并具有弯曲图案的下层引出布线。
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公开(公告)号：US08213209B2
公开(公告)日：2012-07-03
申请号：US12826100
申请日：2010-06-29
IPC分类号： G11C5/00 , G11C17/18 , G11C8/00 , H01L23/52 , H01L21/336
CPC分类号： H01L23/5256 , G11C17/16 , H01L22/14 , H01L22/20 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： In a method of manufacturing a semiconductor device, element properties of an element property extraction pattern formed on a semiconductor wafer is extracted as element properties of a current control element corresponding to the element property extraction pattern. A supply energy to the current control element is set which is formed between nodes on the semiconductor wafer, based on the extracted element properties. The set supply energy is supplied to the current control element to irreversible control an electrical connection between the nodes through the device breakdown by the current control element.
摘要翻译： 在制造半导体器件的方法中，提取形成在半导体晶片上的元素特性提取图案的元素性质作为与元素特性提取图案对应的电流控制元件的元素特性。 基于所提取的元件特性，设置在半导体晶片上的节点之间形成对电流控制元件的供给能量。 设定的供给能量被提供给电流控制元件，以通过由电流控制元件击穿的装置不可逆地控制节点之间的电连接。
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公开(公告)号：US20100096724A1
公开(公告)日：2010-04-22
申请号：US12588223
申请日：2009-10-08
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device (200) includes an electric fuse (100) including: an upper layer fuse interconnect (112) formed on a substrate (not shown); a lower layer fuse interconnect (122); and a via (130) which is connected to one end of the upper layer fuse interconnect (112) and connects the upper layer fuse interconnect (112) and the lower layer fuse interconnect (122). The upper fuse interconnect (112) includes a width varying region (118) having a small interconnect width on a side of the one end.
摘要翻译： 半导体器件（200）包括电熔丝（100），包括：形成在衬底（未示出）上的上层熔丝互连（112）; 下层熔丝互连（122）; 以及连接到上层熔丝互连（112）的一端并连接上层熔丝互连（112）和下层熔丝互连（122）的通孔（130）。 上部熔丝互连（112）包括在一端的一侧具有小互连宽度的宽度变化区（118）。
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6.发明授权Semiconductor device having an anti-fuse element and a transistor with a pocket region 有权具有抗熔丝元件的半导体器件和具有口袋区域的晶体管公开(公告)号：US08519508B2
公开(公告)日：2013-08-27
申请号：US12938662
申请日：2010-11-03
IPC分类号： H01L21/336
CPC分类号： H01L27/0629 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a conventional NMOS transistor and an NMOS transistor functioning as an anti-fuse element and having an n type channel region. The conventional NMOS transistor is equipped with an n type extension region and a p type pocket region, while the anti-fuse element is not equipped with an extension region and a pocket region. This makes it possible to improve the performance of the transistor and at the same time improve the characteristics of the anti-fuse element after breakdown of its gate dielectric film.
摘要翻译： 半导体器件具有常规的NMOS晶体管和用作反熔丝元件并具有n型沟道区的NMOS晶体管。 传统的NMOS晶体管配备有n型延伸区域和p型袋区域，而反熔丝元件没有配备延伸区域和口袋区域。 这使得可以提高晶体管的性能，同时提高其栅极电介质膜击穿之后的抗熔丝元件的特性。
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公开(公告)号：US08274134B2
公开(公告)日：2012-09-25
申请号：US12588223
申请日：2009-10-08
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device (200) includes an electric fuse (100) including: an upper layer fuse interconnect (112) formed on a substrate (not shown); a lower layer fuse interconnect (122); and a via (130) which is connected to one end of the upper layer fuse interconnect (112) and connects the upper layer fuse interconnect (112) and the lower layer fuse interconnect (122). The upper fuse interconnect (112) includes a width varying region (118) having a small interconnect width on a side of the one end.
摘要翻译： 半导体器件（200）包括电熔丝（100），包括：形成在衬底（未示出）上的上层熔丝互连（112）; 下层熔丝互连（122）; 以及连接到上层熔丝互连（112）的一端并连接上层熔丝互连（112）和下层熔丝互连（122）的通孔（130）。 上部熔丝互连（112）包括在一端的一侧具有小互连宽度的宽度变化区（118）。
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8.发明申请Semiconductor device having memory unit, method of writing to or reading from memory unit, and semiconductor device manufacturing method 有权具有存储单元的半导体器件，写入或从存储单元读取的方法以及半导体器件制造方法公开(公告)号：US20120044741A1
公开(公告)日：2012-02-23
申请号：US13067773
申请日：2011-06-24
申请人： Hiromichi Takaoka , Kenichi Hidaka , Hiroshi Tsuda , Kiyokazu Ishige , Yoshitaka Kubota , Takuji Onuma
发明人： Hiromichi Takaoka , Kenichi Hidaka , Hiroshi Tsuda , Kiyokazu Ishige , Yoshitaka Kubota , Takuji Onuma
IPC分类号： G11C17/08 , H01L21/336 , H01L27/088
CPC分类号： H01L27/101 , G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.
摘要翻译： 第一半导体器件形成在衬底上并且包括第一绝缘膜，第一电极和第一扩散层。 第二半导体器件形成在衬底上并且包括第二绝缘膜，第二电极和第二扩散层。 第二电极耦合到第一电极。 控制晶体管允许源极和漏极中的一个耦合到第一电极和第二电极，允许源极和漏极中的另一个耦合到位线，并且允许栅电极耦合到 一个字线。 第一电位控制线耦合到第一扩散层并控制第一扩散层的电位。 第二电位控制线耦合到第二扩散层并控制第二扩散层的电位。
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公开(公告)号：US08982648B2
公开(公告)日：2015-03-17
申请号：US13193186
申请日：2011-07-28
CPC分类号： G11C17/18
摘要： An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit which has first current drive capability and which performs first programming operation and a second programming circuit which has second current drive capability larger than the first current drive capability and which performs second programming operation to follow the first programming operation. In the first programming operation, the first programming circuit breaks down the gate insulating film by applying a first programming voltage between the first terminal and the second terminal. In the second programming operation, the second programming circuit applies a second programming voltage lower than the first programming voltage between the first terminal and the second terminal.
摘要翻译： 由NMOS晶体管或NMOS电容器构成的反熔丝包括耦合到栅电极的第一端子，耦合到扩散层的第二端子和介于栅极电极和扩散层之间的栅极绝缘膜。 编程电路包括具有第一电流驱动能力并执行第一编程操作的第一编程电路和具有大于第一电流驱动能力的第二电流驱动能力的第二编程电路，并且执行第二编程操作以跟随第一编程操作 。 在第一编程操作中，第一编程电路通过在第一端子和第二端子之间施加第一编程电压来分解栅极绝缘膜。 在第二编程操作中，第二编程电路在第一端子和第二端子之间施加低于第一编程电压的第二编程电压。
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10.发明授权Semiconductor device having memory unit, method of writing to or reading from memory unit, and semiconductor device manufacturing method 有权具有存储单元的半导体器件，写入或从存储器单元读取的方法以及半导体器件制造方法公开(公告)号：US08675385B2
公开(公告)日：2014-03-18
申请号：US13067773
申请日：2011-06-24
申请人： Hiromichi Takaoka , Kenichi Hidaka , Hiroshi Tsuda , Kiyokazu Ishige , Yoshitaka Kubota , Takuji Onuma
发明人： Hiromichi Takaoka , Kenichi Hidaka , Hiroshi Tsuda , Kiyokazu Ishige , Yoshitaka Kubota , Takuji Onuma
IPC分类号： G11C17/08
CPC分类号： H01L27/101 , G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.
摘要翻译： 第一半导体器件形成在衬底上并且包括第一绝缘膜，第一电极和第一扩散层。 第二半导体器件形成在衬底上并且包括第二绝缘膜，第二电极和第二扩散层。 第二电极耦合到第一电极。 控制晶体管允许源极和漏极中的一个耦合到第一电极和第二电极，允许源极和漏极中的另一个耦合到位线，并且允许栅电极耦合到 一个字线。 第一电位控制线耦合到第一扩散层并控制第一扩散层的电位。 第二电位控制线耦合到第二扩散层并控制第二扩散层的电位。
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