公开(公告)号：USRE32800E

公开(公告)日：1988-12-13

申请号：US053269

申请日：1987-05-21

Applicant: Yu-Pin Han ,  Tsiu C. Chan

Inventor： Yu-Pin Han ,  Tsiu C. Chan

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66598 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/78

Abstract: A short channel metal oxide semiconductor transistor device is processed without undesirable short channel effects, such as V.sub.T falloff and with a reasonable source-drain operating voltage support. In a substrate lightly doped with P-type conductivity material and source and drain region heavily doped with an N-type conductivity material, two lightly doped N- regions are disposed between the edge of the gate and the source and drain regions. A channel region is more heavily doped with P-type material than the substrate. Two regions extend from opposite sides of the channel region to an area generally below the two N- regions and above the substrate, which regions are more heavily doped than the channel regions.

公开(公告)号：US4771014A

公开(公告)日：1988-09-13

申请号：US99144

申请日：1987-09-18

Applicant: Fu-Tai Liou ,  Yu-Pin Han ,  Frank R. Bryant

Inventor： Fu-Tai Liou ,  Yu-Pin Han ,  Frank R. Bryant

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L27/00

CPC classification number: H01L21/823878 ,  H01L27/0928

Abstract: A method for making a CMOS integrated circuit device saves on masking steps by using unmasked blanket implantations at various steps of the process, such as setting the threshold voltages of the transistors, forming a lightly doped drain for the N-channel transistor, and for forming the source/drain regions of the N-type transistor.

公开(公告)号：US5801396A

公开(公告)日：1998-09-01

申请号：US488398

申请日：1995-06-07

Applicant: Tsiu Chiu Chan ,  Yu-Pin Han ,  Elmer H. Guritz ,  Richard A. Blanchard

Inventor： Tsiu Chiu Chan ,  Yu-Pin Han ,  Elmer H. Guritz ,  Richard A. Blanchard

IPC: H01L21/8244 ,  H01L27/06 ,  H01L27/092 ,  H01L27/11 ,  H01L29/04

CPC classification number: H01L27/11 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  Y10S257/903 ,  Y10S438/981

Abstract: A CMOS device architecture which includes substrate-gated inverted PMOS transistors, as well as bulk NMOS. The inverted-PMOS channels are formed in a different layer from the NMOS gates, and these layers may even have different compositions. Moreover, the NMOS and inverted-PMOS devices have different gate oxide layers, so the thicknesses can be independently optimized. The drain underlap of the inverted device is defined by a patterning step, so it can be increased for high-voltage operation if desired.

公开(公告)号：US5793094A

公开(公告)日：1998-08-11

申请号：US579780

申请日：1995-12-28

Applicant: Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh ,  Walter D. Parmantie

Inventor： Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh ,  Walter D. Parmantie

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: A method for substantially reducing variations in a programming voltage of an anti-fuse structure formed on an integrated circuit wafer. The anti-fuse structure has a metal-one layer, an anti-fuse layer disposed above the metal-one layer, a oxide layer disposed above the anti-fuse layer, and a via hole in the oxide layer through to the anti-fuse layer for receiving a deposition of a metal-two material. The method includes the step of rendering a selected anti-fuse area susceptible to fuse link formation by reducing a resistivity of the selected anti-fuse area to diffusion of atoms from one of the metal-one layer and the metal-two layer when a programming voltage is applied between the metal one layer and the metal two layer. The selected anti-fuse area is located in the anti-fuse layer and substantially adjacent to and outside of an anti-fuse area directly below the via hole. The method further includes the step of depositing the metal-two material into the via hole.

Abstract translation: 一种用于基本上减少在集成电路晶片上形成的抗熔丝结构的编程电压的变化的方法。 反熔丝结构具有金属一层，设置在金属一层上方的抗熔丝层，设置在抗熔融层上方的氧化物层，以及氧化物层中的通孔到反熔丝 用于接收金属二材料的沉积的层。 该方法包括以下步骤：当编程时，通过降低所选择的反熔丝区域与金属层和金属二层中的一个的原子的扩散，使选择的抗熔丝区域易于熔融链接形成 在金属一层和金属两层之间施加电压。 所选择的反熔丝区域位于反熔丝层中，并且基本上邻近通孔正下方的反熔丝区域的外部。 该方法还包括将金属二材料沉积到通孔中的步骤。

公开(公告)号：US5135888A

公开(公告)日：1992-08-04

申请号：US531014

申请日：1990-05-31

Applicant: Tsiu C. Chan ,  Yu-Pin Han ,  Elmer H. Guritz

Inventor： Tsiu C. Chan ,  Yu-Pin Han ,  Elmer H. Guritz

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/092 ,  H01L27/11

CPC classification number: H01L27/11 ,  H01L27/0605 ,  H01L27/1104 ,  H01L27/1108 ,  H01L28/20 ,  H01L27/1112

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SPRAM cells.

Abstract translation: CMOS SRAM单元在作为数据存储节点的公共节点和电源之间具有多晶硅信号线。 在该多晶硅信号线内制造场效应器件。 场效应器件的沟道通过薄栅电介质与衬底中的有源区域分离，并且衬底内的有源区域用作场效应器件的控制栅极。 这种器件可用于提供用于CMOS SPRAM单元的多晶硅P沟道晶体管。

公开(公告)号：US4981813A

公开(公告)日：1991-01-01

申请号：US279343

申请日：1988-12-02

Applicant: Frank R. Bryant ,  Yu-Pin Han ,  Fu-Tai Liou ,  Tsiu C. Chan

Inventor： Frank R. Bryant ,  Yu-Pin Han ,  Fu-Tai Liou ,  Tsiu C. Chan

IPC: H01L21/32 ,  H01L21/762

CPC classification number: H01L21/76205 ,  H01L21/32

Abstract: Field oxide regions are formed between active regions of a silicon substrate by forming over the substrate a sandwich of silicon dioxide, silicon nitride and silicon dioxide layers, opening the layers to expose a portion of the silicon substrate, removing a layer of the exposed substrate, forming side wall spacers on the edges of the opening, removing a layer of the silicon substrate exposed between the side wall spacers, and then reaching the exposed substrate for the thermal oxidation of the exposed substrate for forming the field oxide region. In those structures in which the field oxide is buried in the substrate as shown in FIG. 12, it may be feasible to use thicker field oxide regions and thereby to reduce the need for the heavily doped surface layer under the field oxide.

Abstract translation: 通过在衬底上形成二氧化硅，氮化硅和二氧化硅层的夹层来形成在硅衬底的有源区之间的场氧化物区域，打开这些层以露出硅衬底的一部分，去除暴露的衬底的一层， 在开口的边缘上形成侧壁间隔物，去除暴露在侧壁间隔物之间​​的硅衬底层，然后到达暴露的衬底，用于暴露衬底的热氧化以形成场氧化物区域。 在如图1所示的那些场地氧化物埋在衬底中的那些结构中。 如图12所示，可以使用较厚的场氧化物区域，从而减少对场氧化物下的重掺杂表面层的需要。

公开(公告)号：US4599118A

公开(公告)日：1986-07-08

申请号：US654281

申请日：1984-09-24

Applicant: Yu-Pin Han ,  Tsiu C. Chan

Inventor： Yu-Pin Han ,  Tsiu C. Chan

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/308

CPC classification number: H01L29/66598 ,  H01L21/265 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7833 ,  Y10S148/082

Abstract: A short channel metal oxide semiconductor transistor device is processed without undesirable short channel effects, such as V.sub.T falloff and with a reasonable source-drain operating voltage support. In a substrate lightly doped with P-type conductivity material and source and drain region heavily doped with an N-type conductivity material, two lightly doped N- regions are disposed between the edge of the gate and the source and drain regions. A channel region is more heavily doped with P-type material than the substrate. Two regions extend from opposite sides of the channel region to an area generally below the two N- regions and above the substrate, which regions are more heavily doped than the channel regions.

Abstract translation: 处理短沟道金属氧化物半导体晶体管器件而没有不期望的短沟道效应，例如VT衰减和合理的源极 - 漏极工作电压支持。 在轻掺杂有P型导电材料的衬底和重掺杂有N型导电材料的源极和漏极区域中，在栅极的边缘与源极和漏极区域之间设置两个轻掺杂的N区。 与衬底相比，沟道区比P型材料更重掺杂。 两个区域从通道区域的相对侧延伸到通常低于两个N-区域并且在衬底上方的区域，这些区域比沟道区域更重掺杂。

公开(公告)号：US5847465A

公开(公告)日：1998-12-08

申请号：US436165

申请日：1995-05-08

Applicant: Fu-Tai Liou ,  Yu-Pin Han

Inventor： Fu-Tai Liou ,  Yu-Pin Han

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L23/48 ,  H01L23/52 ,  H01L27/088 ,  H01L29/40

CPC classification number: H01L29/6659 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/76804 ,  H01L29/41775 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S257/90

Abstract: A method for fabrication of metal to semiconductor contacts results in sloped sidewalls in contact regions. An oxide layer is deposited and etched back to form sidewall spacers. A glass layer is then deposited and heated to reflow. After reflow, an etch back of the glass layer results is sloped sidewalls at contact openings and over steps.

Abstract translation: 金属对半导体接触的制造方法导致接触区域的倾斜侧壁。 沉积氧化物层并回蚀刻以形成侧壁间隔物。 然后沉积玻璃层并加热回流。 在回流之后，玻璃层的回蚀是在接触开口和过度台阶上的倾斜侧壁。

公开(公告)号：US5821558A

公开(公告)日：1998-10-13

申请号：US792791

申请日：1997-02-03

Applicant: Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

Inventor： Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

IPC: H01L21/8246 ,  H01L27/112 ,  H01L29/04 ,  H01L27/02

CPC classification number: H01L27/11206 ,  H01L27/112

Abstract: An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.

Abstract translation: 反熔丝结构包括第一电极，在第一电极上方的增强非晶硅层，以及增强非晶硅层上的第二电极。 通过将中性物质和掺杂剂物质的离子注入到非晶硅的沉积层中形成增强非晶硅层，使得反熔丝结构将在编程状态下具有稳定的导电链路，并且使得其将被 在非编程状态下较不易于断态泄漏。 制造反熔丝结构的方法包括形成下电极，在下电极上沉积非晶硅层，将中性物质和掺杂剂物质离子注入到非晶硅层中，以及在非晶硅层上形成上电极。

公开(公告)号：US5793640A

公开(公告)日：1998-08-11

申请号：US773171

申请日：1996-12-26

Applicant: Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

Inventor： Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

IPC: G01R27/26 ,  G01R27/00

CPC classification number: G01R27/2605

Abstract: A computer-aided method and system are provided for obtaining a measurement of the capacitance value of a device under test (DUT). The complex impedance of a device under test (DUT) is measured at two nearby frequencies using an RLC meter. The two complex impedance values are then stored in a computer readable medium. The DUT is modeled by a programmed computer as a four element RLC model circuit including a resistor and inductor in series with a parallel RC circuit having a single capacitor which represents the capacitance of the DUT. Four equations which describe the electrical characteristics of the four element RLC model circuit are stored in a computer readable medium. The four measured values of complex impedance are substituted by the computer into the four stored equations. Values are obtained for the four individual RLC circuit elements by solving the four equations. The four unknown values are obtained by use of an optimization routine and then stored to a computer readable medium. The value capacitor element representing the capacitance of the DUT is then displayed.

Abstract translation: 提供了一种计算机辅助方法和系统，用于获得待测器件（DUT）的电容值的测量。 被测设备（DUT）的复阻抗使用RLC仪在两个附近的频率下测量。 然后将两个复阻抗值存储在计算机可读介质中。 DUT被编程的计算机建模为四元件RLC模型电路，其包括与表示DUT的电容的单个电容器的并联RC电路串联的电阻器和电感器。 描述四元素RLC模型电路的电特性的四个等式被存储在计算机可读介质中。 复阻抗的四个测量值被计算机代入四个存储的方程。 通过求解四个等式获得四个单独的RLC电路元件的值。 通过使用优化例程获得四个未知值，然后将其存储到计算机可读介质中。 然后显示表示DUT的电容的值电容器元件。