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    Layout Architecture for Improving Circuit Performance
    11.
    发明申请
    Layout Architecture for Improving Circuit Performance 有权
    用于提高电路性能的布局架构

    公开(公告)号：US20090315079A1

    公开(公告)日：2009-12-24

    申请号：US12193354

    申请日：2008-08-18

    申请人： Li-Chun Tien ,  Lee-Chung Lu ,  Yung-Chin Hou ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Sheng-Hsin Chen ,  Ping Chung Li

    发明人： Li-Chun Tien ,  Lee-Chung Lu ,  Yung-Chin Hou ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Sheng-Hsin Chen ,  Ping Chung Li

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/092 ,  H01L27/0207

    摘要： An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.

    摘要翻译： 集成电路结构包括集成电路结构，其包括：包括第一栅电极的PMOS晶体管; 第一源区; 和第一漏区; 包括第二栅电极的NMOS晶体管，其中所述第一栅电极和所述第二栅电极是栅电极条的部分; 第二源区; 和第二漏区。 在PMOS晶体管和NMOS晶体管之间不会形成附加的晶体管。 集成电路还包括连接到第一源极区的VDD电源轨; 连接到第二源区的VSS电力轨; 以及电连接到栅电极条的互连端口。 互连端口位于包括PMOS晶体管，NMOS晶体管以及PMOS晶体管和NMOS晶体管之间的区域的MOS对区域的外侧。 MOS对区域中的栅电极条的部分基本上是直的。

    Methods for cell boundary isolation in double patterning design
    12.
    发明授权
    Methods for cell boundary isolation in double patterning design 有权
    双图案设计中单元边界隔离的方法

    公开(公告)号：US08255837B2

    公开(公告)日：2012-08-28

    申请号：US12616970

    申请日：2009-11-12

    申请人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Yuan-Te Hou ,  Yung-Chin Hou ,  Li-Chun Tien

    发明人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Yuan-Te Hou ,  Yung-Chin Hou ,  Li-Chun Tien

    IPC分类号： G06F17/50

    CPC分类号： G03F1/70 ,  G03F1/00

    摘要： A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.

    摘要翻译： 设计用于芯片布局的双重图案掩模组的方法包括设计标准单元。 在每个标准单元中，所有左边界图案被分配有第一指示符和第二指示符中的一个，并且所有右边图案都被分配有第一指示符和第二指示符中的另外一个。 该方法还包括将标准单元放置在芯片布局的一行中。 从行中的一个标准单元开始，标记单元的指示符更改在整行中传播。 具有第一指示符的标准单元中的所有图案被转移到双图案掩模组的第一掩模。 具有第二指示器的标准单元中的所有图案被转移到双重图案掩模组的第二掩模。

    Standard cell without OD space effect in Y-direction
    13.
    发明授权
    Standard cell without OD space effect in Y-direction 有权
    标准电池在Y方向没有OD空间效应

    公开(公告)号：US07808051B2

    公开(公告)日：2010-10-05

    申请号：US12345372

    申请日：2008-12-29

    申请人： Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    发明人： Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0207 ,  H01L27/11807

    摘要： An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.

    摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底中的第一有源区; 以及在所述半导体衬底中并且具有与所述第一有源区相反的导电类型的第二有源区。 栅电极条在第一和第二有源区之上，分别形成具有第一有源区和第二有源区的第一MOS器件和第二MOS器件。 第一间隔棒位于半导体衬底中并与第一有源区连接。 第一间隔条的至少一部分与第一有源区的一部分相邻并间隔开。 第二间隔杆位于半导体衬底中并连接到第二有源区。 第二间隔杆的至少一部分与第二有源区的一部分相邻并间隔开。

    Structure and System of Mixing Poly Pitch Cell Design under Default Poly Pitch Design Rules
    14.
    发明申请
    Structure and System of Mixing Poly Pitch Cell Design under Default Poly Pitch Design Rules 有权
    混合多节距单元设计在默认多点设计规则下的结构和系统

    公开(公告)号：US20100164614A1

    公开(公告)日：2010-07-01

    申请号：US12347628

    申请日：2008-12-31

    申请人： Yung-Chin Hou ,  Li-Chun Tien ,  Lee-Chung Lu ,  Ping Chung Li ,  Ta-Pen Guo

    发明人： Yung-Chin Hou ,  Li-Chun Tien ,  Lee-Chung Lu ,  Ping Chung Li ,  Ta-Pen Guo

    IPC分类号： H01L25/00

    CPC分类号： G06F17/5072 ,  H01L27/0207 ,  H01L27/11803

    摘要： An integrated circuit including type-1 cells and a type-2 cell is presented. The type-1 cells have poly lines with a default poly pitch. The type-2 cell has poly lines with a non-default poly pitch. A first boundary region has at least one isolation area that lies between the type-1 cells and the type-2 cell in the X-direction. The first boundary region includes at least one merged dummy poly line, wherein the at least one merged dummy poly line has a first portion that complies with the default poly pitch of the type-1 cells and a second portion that complies with the non-default poly pitch of the type-2 cell.

    摘要翻译： 提出了包括1型电池和2型电池的集成电路。 1型电池具有默认聚间距的多线。 2型电池具有具有非默认聚间距的多线。 第一边界区域具有位于X方向上的类型1单元和类型2单元之间的至少一个隔离区域。 第一边界区域包括至少一个合并的虚拟多线，其中所述至少一个合并虚拟多线具有符合类型-1单元的默认多音调的第一部分和符合非默认的第二部分 2型细胞的聚间距。

    Integrated circuit design using DFM-enhanced architecture
    15.
    发明授权
    Integrated circuit design using DFM-enhanced architecture 有权
    采用DFM增强架构的集成电路设计

    公开(公告)号：US08631366B2

    公开(公告)日：2014-01-14

    申请号：US12708242

    申请日：2010-02-18

    申请人： Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

    发明人： Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.

    摘要翻译： 集成电路库包括具有第一左边界和第一右边界的第一标准单元，以及具有第二左边界和第二右边界的第二标准单元。 第一标准细胞和第二标准细胞具有相同的细胞变体。 第一标准单元中的第一有源区具有与第二标准单元中的第二有源区不同的扩散长度。 第一有源区和第二有源区是由表示第一标准单元和第二标准单元的相同电路图的相同分量表示的相应有源区。

    Standard Cell without OD Space Effect in Y-Direction
    17.
    发明申请
    Standard Cell without OD Space Effect in Y-Direction 有权
    标准电池在Y方向没有OD空间效应

    公开(公告)号：US20100078725A1

    公开(公告)日：2010-04-01

    申请号：US12345372

    申请日：2008-12-29

    申请人： Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    发明人： Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    IPC分类号： H01L27/088 ,  H01L29/06

    CPC分类号： H01L27/0207 ,  H01L27/11807

    摘要： An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.

    摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底中的第一有源区; 以及在所述半导体衬底中并且具有与所述第一有源区相反的导电类型的第二有源区。 栅电极条在第一和第二有源区之上，分别形成具有第一有源区和第二有源区的第一MOS器件和第二MOS器件。 第一间隔棒位于半导体衬底中并与第一有源区连接。 第一间隔条的至少一部分与第一有源区的一部分相邻并间隔开。 第二间隔杆位于半导体衬底中并连接到第二有源区。 第二间隔杆的至少一部分与第二有源区的一部分相邻并间隔开。

    Structure and system of mixing poly pitch cell design under default poly pitch design rules
    20.
    发明授权
    Structure and system of mixing poly pitch cell design under default poly pitch design rules 有权
    在默认聚沥青设计规则下混合聚沥青单元设计的结构和系统

    公开(公告)号：US07932566B2

    公开(公告)日：2011-04-26

    申请号：US12347628

    申请日：2008-12-31

    申请人： Yung-Chin Hou ,  Li-Chun Tien ,  Lee-Chung Lu ,  Ping Chung Li ,  Ta-Pen Guo

    发明人： Yung-Chin Hou ,  Li-Chun Tien ,  Lee-Chung Lu ,  Ping Chung Li ,  Ta-Pen Guo

    IPC分类号： H01L25/00

    CPC分类号： G06F17/5072 ,  H01L27/0207 ,  H01L27/11803

    摘要： An integrated circuit including type-1 cells and a type-2 cell is presented. The type-1 cells have poly lines with a default poly pitch. The type-2 cell has poly lines with a non-default poly pitch. A first boundary region has at least one isolation area that lies between the type-1 cells and the type-2 cell in the X-direction. The first boundary region includes at least one merged dummy poly line, wherein the at least one merged dummy poly line has a first portion that complies with the default poly pitch of the type-1 cells and a second portion that complies with the non-default poly pitch of the type-2 cell.

    摘要翻译： 提出了包括1型电池和2型电池的集成电路。 1型电池具有默认聚间距的多线。 2型电池具有具有非默认聚间距的多线。 第一边界区域具有位于X方向上的类型1单元和类型2单元之间的至少一个隔离区域。 第一边界区域包括至少一个合并的虚拟多线，其中所述至少一个合并虚拟多线具有符合类型-1单元的默认多音调的第一部分和符合非默认的第二部分 2型细胞的聚间距。