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101 条记录 (耗时 0.031 秒)

    Cell architecture and method
    6.
    发明授权
    Cell architecture and method 有权
    单元架构和方法

    公开(公告)号：US08356262B1

    公开(公告)日：2013-01-15

    申请号：US13207506

    申请日：2011-08-11

    申请人： Lee-Chung Lu ,  Li-Chun Tien ,  Shyue-Shyh Lin ,  Zhe-Wei Jiang

    发明人： Lee-Chung Lu ,  Li-Chun Tien ,  Shyue-Shyh Lin ,  Zhe-Wei Jiang

    IPC分类号： G06F17/50 ,  H01L29/40 ,  H01L23/48 ,  H01L23/52 ,  H01L21/44

    CPC分类号： G03F1/70 ,  G06F17/504 ,  G06F17/5072 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method includes selecting a cell stored in a non-transient computer readable storage medium, arranging a plurality of the cells on a model of a semiconductor device, and creating a mask for the semiconductor device based on the model of the semiconductor device. The cell is designed according to a design rule in which a first power-supply-connection via satisfies a criterion from the group consisting of: i) the first power-supply-connection via is spaced apart from a second power-supply-connection via by a distance that is greater than a threshold distance such that the cell can be fabricated by a single-photolithography single-etch process, or ii) the first power-supply-connection via is coupled to first and second substantially parallel conductive lines that extend along directly adjacent tracks.

    摘要翻译： 一种方法包括：选择存储在非瞬态计算机可读存储介质中的单元，将多个单元布置在半导体器件的模型上，以及基于半导体器件的模型为半导体器件创建掩模。 电池根据设计规则设计，其中第一电源连接通孔满足以下组的标准：i）第一电源连接通孔与第二电源连接通路间隔开 距离大于阈值距离，使得可以通过单光刻单蚀刻工艺制造单元，或者ii）第一电源连接通孔耦合到第一和第二基本平行的导线，其延伸 沿着直接相邻的轨道。

    Integrated circuit design using DFM-enhanced architecture
    7.
    发明授权
    Integrated circuit design using DFM-enhanced architecture 有权
    采用DFM增强架构的集成电路设计

    公开(公告)号：US08631366B2

    公开(公告)日：2014-01-14

    申请号：US12708242

    申请日：2010-02-18

    申请人： Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

    发明人： Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.

    摘要翻译： 集成电路库包括具有第一左边界和第一右边界的第一标准单元，以及具有第二左边界和第二右边界的第二标准单元。 第一标准细胞和第二标准细胞具有相同的细胞变体。 第一标准单元中的第一有源区具有与第二标准单元中的第二有源区不同的扩散长度。 第一有源区和第二有源区是由表示第一标准单元和第二标准单元的相同电路图的相同分量表示的相应有源区。

    Standard Cell without OD Space Effect in Y-Direction
    8.
    发明申请
    Standard Cell without OD Space Effect in Y-Direction 有权
    标准电池在Y方向没有OD空间效应

    公开(公告)号：US20100078725A1

    公开(公告)日：2010-04-01

    申请号：US12345372

    申请日：2008-12-29

    申请人： Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    发明人： Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    IPC分类号： H01L27/088 ,  H01L29/06

    CPC分类号： H01L27/0207 ,  H01L27/11807

    摘要： An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.

    摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底中的第一有源区; 以及在所述半导体衬底中并且具有与所述第一有源区相反的导电类型的第二有源区。 栅电极条在第一和第二有源区之上，分别形成具有第一有源区和第二有源区的第一MOS器件和第二MOS器件。 第一间隔棒位于半导体衬底中并与第一有源区连接。 第一间隔条的至少一部分与第一有源区的一部分相邻并间隔开。 第二间隔杆位于半导体衬底中并连接到第二有源区。 第二间隔杆的至少一部分与第二有源区的一部分相邻并间隔开。

    Structure and system of mixing poly pitch cell design under default poly pitch design rules
    9.
    发明授权
    Structure and system of mixing poly pitch cell design under default poly pitch design rules 有权
    在默认聚沥青设计规则下混合聚沥青单元设计的结构和系统

    公开(公告)号：US07932566B2

    公开(公告)日：2011-04-26

    申请号：US12347628

    申请日：2008-12-31

    申请人： Yung-Chin Hou ,  Li-Chun Tien ,  Lee-Chung Lu ,  Ping Chung Li ,  Ta-Pen Guo

    发明人： Yung-Chin Hou ,  Li-Chun Tien ,  Lee-Chung Lu ,  Ping Chung Li ,  Ta-Pen Guo

    IPC分类号： H01L25/00

    CPC分类号： G06F17/5072 ,  H01L27/0207 ,  H01L27/11803

    摘要： An integrated circuit including type-1 cells and a type-2 cell is presented. The type-1 cells have poly lines with a default poly pitch. The type-2 cell has poly lines with a non-default poly pitch. A first boundary region has at least one isolation area that lies between the type-1 cells and the type-2 cell in the X-direction. The first boundary region includes at least one merged dummy poly line, wherein the at least one merged dummy poly line has a first portion that complies with the default poly pitch of the type-1 cells and a second portion that complies with the non-default poly pitch of the type-2 cell.

    摘要翻译： 提出了包括1型电池和2型电池的集成电路。 1型电池具有默认聚间距的多线。 2型电池具有具有非默认聚间距的多线。 第一边界区域具有位于X方向上的类型1单元和类型2单元之间的至少一个隔离区域。 第一边界区域包括至少一个合并的虚拟多线，其中所述至少一个合并虚拟多线具有符合类型-1单元的默认多音调的第一部分和符合非默认的第二部分 2型细胞的聚间距。

    NOVEL LAYOUT ARCHITECTURE FOR PERFORMANCE ENHANCEMENT
    10.
    发明申请
    NOVEL LAYOUT ARCHITECTURE FOR PERFORMANCE ENHANCEMENT 审中-公开
    性能增强的新型布局架构

    公开(公告)号：US20100127333A1

    公开(公告)日：2010-05-27

    申请号：US12276172

    申请日：2008-11-21

    申请人： Yung-Chin Hou ,  Ta-Pen Guo ,  Harry Chuang ,  Carlos H. Diaz ,  Lee-Chung Lu ,  Li-Chun Tien ,  Oscar M. K. Law ,  Chih-Chiang Chang ,  Chun-Hui Tai ,  Jonathan Lee

    发明人： Yung-Chin Hou ,  Ta-Pen Guo ,  Harry Chuang ,  Carlos H. Diaz ,  Lee-Chung Lu ,  Li-Chun Tien ,  Oscar M. K. Law ,  Chih-Chiang Chang ,  Chun-Hui Tai ,  Jonathan Lee

    IPC分类号： H01L27/092 ,  H01L27/088

    CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823481

    摘要： The present disclosure provides an integrated circuit. The integrated circuit includes an active region in a semiconductor substrate; a first field effect transistor (FET) disposed in the active region; and an isolation structure disposed in the active region. The FET includes a first gate; a first source formed in the active region and disposed on a first region adjacent the first gate from a first side; and a first drain formed in the active region and disposed on a second region adjacent the first gate from a second side. The isolation structure includes an isolation gate disposed adjacent the first drain; and an isolation source formed in the active region and disposed adjacent the isolation gate such that the isolation source and the first drain are on different sides of the isolation gate.

    摘要翻译： 本发明提供集成电路。 集成电路包括半导体衬底中的有源区; 设置在有源区中的第一场效应晶体管（FET） 以及设置在有源区域中的隔离结构。 FET包括第一栅极; 形成在所述有源区中并且从第一侧设置在与所述第一栅极相邻的第一区域上的第一源极; 以及形成在所述有源区中并且从第二侧设置在与所述第一栅极相邻的第二区域上的第一漏极。 隔离结构包括邻近第一漏极设置的隔离栅极; 以及隔离源，形成在所述有源区中并邻近所述隔离栅设置，使得所述隔离源和所述第一漏极位于所述隔离栅极的不同侧上。