公开(公告)号：US20110102086A1

公开(公告)日：2011-05-05

申请号：US12917652

申请日：2010-11-02

申请人： Yu-Wei LIN ,  Yung-Chow PENG

发明人： Yu-Wei LIN ,  Yung-Chow PENG

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/45475 ,  H03F3/45632 ,  H03F3/45928 ,  H03F2203/45512 ,  H03F2203/45588

摘要： A circuit provides a first current corresponding to the differential input Inn and Inp, and a second current corresponding to the common mode input Vcm. The circuit then mirrors the differential current and the common mode current to a third current and a fourth current. Based on the difference between the mirrored differential current and the mirrored common mode current, the circuit pulls up or pulls down these currents to balance the corresponding difference between the differential input and the common mode input. In effect, the circuit adjusts the input common mode voltage to a desired level, without providing an opportunity for it to rise to an unwanted level.

摘要翻译： 电路提供对应于差分输入Inn和Inp的第一电流，以及对应于共模输入Vcm的第二电流。 电路然后将差分电流和共模电流反射到第三电流和第四电流。 基于镜像差分电流和镜像共模电流之间的差异，电路拉起或拉下这些电流，以平衡差分输入和共模输入之间的相应差值。 实际上，该电路将输入共模电压调整到期望的电平，而不给它提供上升到不需要的电平的机会。

公开(公告)号：US20110057826A1

公开(公告)日：2011-03-10

申请号：US12856993

申请日：2010-08-16

申请人： Yung-Chow PENG ,  Wen-Hung HUANG ,  Yu-Wei LIN

发明人： Yung-Chow PENG ,  Wen-Hung HUANG ,  Yu-Wei LIN

IPC分类号： H03M1/12

CPC分类号： H03M1/002 ,  B81B7/008 ,  H03M1/0626 ,  H03M1/12 ,  H03M3/30

摘要： A micro-electro-mechanical system (MEMS) includes a micro-mechanical structure that is capable of generating a first electrical signal. An analog-to-digital converter (ADC) is coupled with the micro-mechanical structure. The MEMS is free from including any amplifier between the micro-mechanical structure and the ADC.

摘要翻译： 微电子机械系统（MEMS）包括能够产生第一电信号的微机械结构。 模数转换器（ADC）与微机械结构耦合。 MEMS不包括微机械结构和ADC之间的任何放大器。

公开(公告)号：US20130311957A1

公开(公告)日：2013-11-21

申请号：US13475853

申请日：2012-05-18

申请人： Chih-Hsien CHANG ,  Yung-Chow PENG ,  Fu-Lung HSUEH

发明人： Chih-Hsien CHANG ,  Yung-Chow PENG ,  Fu-Lung HSUEH

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/00 ,  G06F17/5009 ,  G06F17/5045 ,  G06F17/5068 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00

摘要： A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured to extract the pre-coloring information from the netlist file. A layout design tool, included in the circuit design system, is configured to design at least one mask based on the schematic information and the pre-coloring information. The circuit design system further includes a layout versus schematic comparison tool configured to compare the at least one mask to the schematic information and the pre-coloring information.

摘要翻译： 电路设计系统包括被配置为产生电路的示意图信息和预着色信息的示意性设计工具。 电路设计系统还包括被配置为在非暂时计算机可读介质上存储原理图信息和预着色信息的网表文件，以及被配置为从网表文件中提取预着色信息的提取工具。 包括在电路设计系统中的布局设计工具被配置为基于原理图信息和预着色信息设计至少一个掩模。 电路设计系统还包括布局与示意性比较工具，其被配置为将至少一个掩模与示意图信息和预着色信息进行比较。

公开(公告)号：US20110090198A1

公开(公告)日：2011-04-21

申请号：US12582107

申请日：2009-10-20

申请人： Fu-Lung HSUEH ,  Yung-Chow PENG ,  Kuo-Liang DENG

发明人： Fu-Lung HSUEH ,  Yung-Chow PENG ,  Kuo-Liang DENG

IPC分类号： G09G5/00 ,  H03M1/66 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2320/02 ,  G09G2330/021

摘要： A method includes outputting a first signal from a first DAC decoder circuit in response to receiving a first number of bits of a digital control signal, outputting a second signal from a second DAC decoder circuit in response to receiving a second number of bits of the digital control signal, and alternately outputting one of the first and second signals to an LCD column from a buffer coupled to the first and second DAC decoder circuits. The first signal has a voltage level equal to one of a first plurality of voltage levels received at one of a first plurality of inputs of the first DAC decoder circuit. The second signal has a voltage level equal to one of a second plurality of voltage levels received at one of a second plurality of inputs of the second DAC decoder circuit.

摘要翻译： 一种方法包括响应于接收数字控制信号的第一位数而输出来自第一DAC解码器电路的第一信号，响应于接收到数字控制信号的第二位数而从第二DAC解码器电路输出第二信号 并且从耦合到第一和第二DAC解码器电路的缓冲器交替地将第一和第二信号之一输出到LCD列。 第一信号具有等于在第一DAC解码器电路的第一多个输入端之一处接收的第一多个电压电平之一的电压电平。 第二信号具有等于在第二DAC解码器电路的第二多个输入端之一处接收的第二多个电压电平之一的电压电平。