公开(公告)号：US20080315313A1

公开(公告)日：2008-12-25

申请号：US11866693

申请日：2007-10-03

申请人： Yasuo YAMAGUCHI ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo YAMAGUCHI ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化膜彼此隔离SOI层中的晶体管形成区域。 在部分氧化膜的下部形成有p型阱区，其将NMOS晶体管彼此隔离，并且在部分氧化膜的下部形成n型阱区，其将PMOS晶体管彼此隔离。 p型阱区域和n型阱区域在部分氧化膜的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域接触。 形成在层间绝缘膜上的互连层通过设置在层间绝缘膜中的体接触电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US20070138560A1

公开(公告)日：2007-06-21

申请号：US11677956

申请日：2007-02-22

申请人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

发明人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

IPC分类号： H01L27/12 ,  H01L29/94

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.

摘要翻译： 在硅层（4）的上表面中选择性地形成部分沟槽型隔离绝缘膜（5）。 电源线（21）形成在隔离绝缘膜（5）的上方。 在电源线（21）的下方，在隔离绝缘膜（5）上形成到达绝缘膜（3）的上表面的完全隔离部（23）。 换句话说，半导体器件包括完全隔离绝缘膜，其形成为从硅层（4）的上表面延伸并到达电源线（21）下方的绝缘膜（3）的上表面 ）。 利用这种结构，可以获得能够抑制由电源线的电位变化引起的体区的电位变化的半导体器件。

公开(公告)号：US07193272B2

公开(公告)日：2007-03-20

申请号：US11108843

申请日：2005-04-19

申请人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

发明人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.

摘要翻译： 在硅层（4）的上表面中选择性地形成部分沟槽型隔离绝缘膜（5）。 电源线（21）形成在隔离绝缘膜（5）的上方。 在电源线（21）的下方，在隔离绝缘膜（5）上形成到达绝缘膜（3）的上表面的完全隔离部（23）。 换句话说，半导体器件包括完全隔离绝缘膜，其形成为从硅层（4）的上表面延伸并到达电源线（21）下方的绝缘膜（3）的上表面 ）。 利用这种结构，可以获得能够抑制由电源线的电位变化引起的体区的电位变化的半导体器件。

公开(公告)号：US06958266B2

公开(公告)日：2005-10-25

申请号：US10120485

申请日：2002-04-12

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

公开(公告)号：US20050037524A1

公开(公告)日：2005-02-17

申请号：US10949451

申请日：2004-09-27

申请人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

发明人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

IPC分类号： H01L21/66 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612

摘要： The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

公开(公告)号：US20060249756A1

公开(公告)日：2006-11-09

申请号：US11481799

申请日：2006-07-07

申请人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

发明人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

IPC分类号： H01L29/768

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612

摘要： A semiconductor device includes a plurality of circuit portions of different functions each constructed by including a MOS transistor on an SOI substrate obtained by sequentially stacking a semiconductor substrate, a buried insulating film and a semiconductor layer. The semiconductor device includes first and second portions. The first circuit portion is isolated by being surrounded with a first insulating film provided on an upper portion of the semiconductor layer and a second insulating film penetrating the semiconductor layer to reach the buried insulating film.

摘要翻译： 半导体器件包括多个不同功能的电路部分，每个电路部分通过在通过顺序地堆叠半导体衬底，埋入绝缘膜和半导体层而获得的SOI衬底上包括MOS晶体管构成。 该半导体器件包括第一和第二部分。 第一电路部分通过被设置在半导体层的上部上的第一绝缘膜和穿过半导体层的第二绝缘膜包围而被隔离，以到达掩埋绝缘膜。

公开(公告)号：US06841400B2

公开(公告)日：2005-01-11

申请号：US10216363

申请日：2002-08-12

申请人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

发明人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

IPC分类号： H01L21/66 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612

摘要： The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

摘要翻译： 本发明涉及制造半导体器件的方法的改进，其中通过防止在有源区中形成沟道阻挡注入层来避免晶体管特性的劣化。 在图案化氮化膜（22）之后，测量SOI层3的厚度（S2），并且通过使用测量结果，确定用于SOI层3的蚀刻条件（蚀刻时间等）（S3）。 为了测量SOI层3的厚度，使用用线偏振光照射物质表面的光谱椭偏仪，并观察到由物质表面反射的椭圆偏振光就足够了。 使用所确定的蚀刻条件，并且通过使用图案化氮化物膜22作为蚀刻掩模形成沟槽TR2（S4）。

公开(公告)号：US07144764B2

公开(公告)日：2006-12-05

申请号：US10949451

申请日：2004-09-27

申请人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

发明人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

IPC分类号： H01L21/762

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612

摘要： The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

摘要翻译： 本发明涉及制造半导体器件的方法的改进，其中通过防止在有源区中形成沟道阻挡注入层来避免晶体管特性的劣化。 在图案化氮化膜（22）之后，测量SOI层3的厚度（S 2），并且通过使用测量结果，确定用于SOI层3的蚀刻条件（蚀刻时间等）（S 3） 。 为了测量SOI层3的厚度，使用用线偏振光照射物质表面的光谱椭偏仪，并观察到由物质表面反射的椭圆偏振光就足够了。 使用所确定的蚀刻条件，并且通过使用图案化的氮化物膜22作为蚀刻掩模形成沟槽TR 2（S 4）。

公开(公告)号：US20070007595A1

公开(公告)日：2007-01-11

申请号：US11520640

申请日：2006-09-14

申请人： Yuuichi Hirano ,  Shigenobu Maeda ,  Takuji Matsumoto ,  Takashi Ipposhi ,  Shigeto Maegawa

发明人： Yuuichi Hirano ,  Shigenobu Maeda ,  Takuji Matsumoto ,  Takashi Ipposhi ,  Shigeto Maegawa

IPC分类号： H01L27/12

CPC分类号： H01L23/481 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/78639 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A back metal (18) is formed on an under surface (back surface) of the support substrate (10) and said back metal (18) is connected with the wiring (17a) through a heat radiating plug (16). The contact plug (15a), the heat radiating plug (16) the wiring (17a) and the back metal (18) is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film (11) and the support substrate (10).

摘要翻译： 半导体器件具有通过支撑衬底（10）上的氧化硅膜（11）形成的硅层（SOI层）（12）。 在SOI层（12）中形成晶体管（T 1）。 布线（17a）通过接触插塞（15A）与晶体管（T 1）的源极连接。 背衬金属（18）形成在支撑基板（10）的下表面（背面）上，所述背金属（18）通过散热塞（16）与布线（17a）连接。 接触塞（15A），散热塞（16），布线（17a）和背金属（18）由诸如铝，钨等的金属制成，其具有比 氧化硅膜（11）和支撑基板（10）。

公开(公告)号：US07541644B2

公开(公告)日：2009-06-02

申请号：US10793841

申请日：2004-03-08

申请人： Yuuichi Hirano ,  Shigenobu Maeda ,  Takuji Matsumoto ,  Takashi Ipposhi ,  Shigeto Maegawa

发明人： Yuuichi Hirano ,  Shigenobu Maeda ,  Takuji Matsumoto ,  Takashi Ipposhi ,  Shigeto Maegawa

IPC分类号： H01L29/72

CPC分类号： H01L23/481 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/78639 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A back metal (18) is formed on an under surface (back surface) of the support substrate (10) and said back metal (18) is connected with the wiring (17a) through a heat radiating plug (16). The contact plug (15a), the heat radiating plug (16) the wiring (17a) and the back metal (18) is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film (11) and the support substrate (10).

摘要翻译： 半导体器件具有通过支撑衬底（10）上的氧化硅膜（11）形成的硅层（SOI层）（12）。 在SOI层（12）中形成晶体管（T1）。 布线（17a）通过接触插塞（15a）与晶体管（T1）的源极连接。 背衬金属（18）形成在支撑基板（10）的下表面（背面）上，背面金属（18）通过散热塞（16）与布线17a连接。 接触插头（15a），散热塞（16），布线（17a）和背金属（18）由诸如铝，钨等的金属制成，其具有比硅的热导率更高的导热性 氧化膜（11）和支撑基板（10）。