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    Stack tracker
    12.
    发明申请
    Stack tracker 审中-公开
    堆栈跟踪器

    公开(公告)号：US20070130448A1

    公开(公告)日：2007-06-07

    申请号：US11291378

    申请日：2005-12-01

    申请人： Stephan Jourdan ,  Mark Davis ,  Sebastien Hily

    发明人： Stephan Jourdan ,  Mark Davis ,  Sebastien Hily

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3836 ,  G06F9/30043 ,  G06F9/30134 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

    摘要： Methods and apparatus to identify memory communications are described. In one embodiment, an access to a stack pointer is monitored, e.g., to maintain a stack tracker structure. The information stored in the stack tracker structure may be utilized to generate a distance value corresponding to a relative distance between a load instruction and a previous store instruction.

    摘要翻译： 描述了识别存储器通信的方法和装置。 在一个实施例中，监视对堆栈指针的访问，例如，以维持堆栈跟踪器结构。 存储在堆栈跟踪器结构中的信息可以用于产生对应于加载指令和先前存储指令之间的相对距离的距离值。

    Predicting instruction branches with a plurality of global predictors
    13.
    发明申请
    Predicting instruction branches with a plurality of global predictors 失效
    用多个全局预测器预测指令分支

    公开(公告)号：US20050149707A1

    公开(公告)日：2005-07-07

    申请号：US10743711

    申请日：2003-12-24

    申请人： Stephan Jourdan ,  Mark Davis ,  Pierre Michaud

    发明人： Stephan Jourdan ,  Mark Davis ,  Pierre Michaud

    IPC分类号： G06F9/00 ,  G06F9/38

    CPC分类号： G06F9/3848

    摘要： Systems and methods of processing branch instructions provide for a bimodal predictor and a plurality of global predictors. The bimodal predictor is coupled to a prediction selector, where the bimodal predictor generates a bimodal prediction for branch instructions. The plurality of global predictors is coupled to the prediction selector, where each global predictor generates a corresponding global prediction for a branch instruction using different history or stew lengths. The prediction selector selects branch predictions from the bimodal prediction and the global predictions in order to arbitrate between predictors. The arbitration, update, and allocation schemes are designed to choose the most accurate predictor for each branch. Lower level predictors are used as filters to increase effective predictor capacity. Allocate and update schemes minimize aliasing between predictors. Branch predictors incorporating a plurality of global predictors in this fashion are more adaptive than conventional predictors with fixed branch history lengths and are able to achieve superior accuracy.

    摘要翻译： 处理分支指令的系统和方法提供双峰预测器和多个全局预测器。 双模态预测器耦合到预测选择器，其中双模态预测器生成分支指令的双峰预测。 多个全局预测器被耦合到预测选择器，其中每个全局预测器使用不同的历史或炖长度来生成对于分支指令的相应的全局预测。 预测选择器从双模预测和全局预测中选择分支预测，以便在预测器之间进行仲裁。 仲裁，更新和分配方案旨在为每个分支选择最准确的预测器。 较低级别的预测变量被用作过滤器来增加有效的预测能力。 分配和更新方案使预测变量之间的混叠最小化。 以这种方式并入多个全局预测变量的分支预测器比具有固定分支历史长度的传统预测变量更适应，并且能够实现更高的精度。

    Memory array with staged output
    14.
    发明申请
    Memory array with staged output 失效
    具有分段输出的内存阵列

    公开(公告)号：US20050135178A1

    公开(公告)日：2005-06-23

    申请号：US10739268

    申请日：2003-12-19

    申请人： Stephan Jourdan ,  Boyd Phelps ,  Chris Yuker

    发明人： Stephan Jourdan ,  Boyd Phelps ,  Chris Yuker

    IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C11/413

    CPC分类号： G11C7/1075 ,  G11C11/413

    摘要： Embodiments of the present invention provide a method and system for staging the data output from an addressable memory location as a plurality of fields. In embodiments, each field of a data item that is stored at an address may be output during a different clock cycle. In further embodiments, the most time critical field may be output first.

    摘要翻译： 本发明的实施例提供了一种用于将从可寻址存储器位置输出的数据分段为多个场的方法和系统。 在实施例中，可以在不同的时钟周期期间输出存储在地址处的数据项的每个字段。 在另外的实施例中，可以首先输出大多数时间关键字段。

    Predicting instruction branches with independent checking predictions
    15.
    发明申请
    Predicting instruction branches with independent checking predictions 审中-公开
    用独立检查预测预测指令分支

    公开(公告)号：US20050132174A1

    公开(公告)日：2005-06-16

    申请号：US10735675

    申请日：2003-12-16

    申请人： Stephan Jourdan ,  Boyd Phelps ,  Mark Davis

    发明人： Stephan Jourdan ,  Boyd Phelps ,  Mark Davis

    IPC分类号： G06F9/00 ,  G06F9/38

    CPC分类号： G06F9/3806 ,  G06F9/3848 ,  G06F9/3851

    摘要： Systems and methods of predicting instruction branches provide for independent checking predictions and dynamic next-line predictions. Next-line predictions may also have a latency that is a plurality of clock cycles, where the next line predictions include group predictions. Each group prediction includes a plurality of target addresses corresponding to their plurality of clock cycles. The plurality of target addresses can include a leaf target and one or more intermediate targets, where the leaf target defines a target address of the group prediction.

    摘要翻译： 预测指令分支的系统和方法提供独立的检查预测和动态下一行预测。 下一行预测还可能具有多个时钟周期的延迟，其中下一行预测包括组预测。 每个组预测包括对应于它们的多个时钟周期的多个目标地址。 多个目标地址可以包括叶目标和一个或多个中间目标，其中叶目标定义组预测的目标地址。

    Method and apparatus for partitioned pipelined fetching of multiple execution threads
    17.
    发明授权
    Method and apparatus for partitioned pipelined fetching of multiple execution threads 失效

    公开(公告)号：US07454596B2

    公开(公告)日：2008-11-18

    申请号：US11479345

    申请日：2006-06-29

    申请人： Stephan Jourdan ,  Robert Hinton

    发明人： Stephan Jourdan ,  Robert Hinton

    IPC分类号： G06F9/38 ,  G06F15/00

    CPC分类号： G06F9/3802 ,  G06F9/3851

    摘要： Methods and apparatus for partitioning a microprocessor pipeline to support pipelined branch prediction and instruction fetching of multiple execution threads. A thread selection stage selects a thread from a plurality of execution threads. In one embodiment, storage in a branch prediction output queue is pre-allocated to a portion of the thread in one branch prediction stage in order to prevent stalling of subsequent stages in the branch prediction pipeline. In another embodiment, an instruction fetch stage fetches instructions at a fetch address corresponding to a portion of the selected thread. Another instruction fetch stage stores the instruction data in an instruction fetch output queue if enough storage is available. Otherwise, instruction fetch stages corresponding to the selected thread are invalidated and refetched to avoid stalling preceding stages in the instruction fetch pipeline, which may be fetching instructions of another thread.

    Overriding a static prediction
    19.
    发明申请
    Overriding a static prediction 有权
    覆盖静态预测

    公开(公告)号：US20080059779A1

    公开(公告)日：2008-03-06

    申请号：US11513709

    申请日：2006-08-31

    申请人： Mark C. Davis ,  Stephan Jourdan ,  Robert L. Hinton ,  Boyd S. Phelps

    发明人： Mark C. Davis ,  Stephan Jourdan ,  Robert L. Hinton ,  Boyd S. Phelps

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3806 ,  G06F9/3846 ,  G06F9/3848

    摘要： In one embodiment, the present invention includes a method for determining if an entry corresponding to a prediction address is present in a first predictor, and overriding a prediction output from a second predictor corresponding to the prediction address if the entry is present in the first predictor. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括一种用于确定对应于预测地址的条目是否存在于第一预测器中的方法，以及如果该条目存在于第一预测器中则覆盖与预测地址对应的第二预测器的预测输出 。 描述和要求保护其他实施例。

    Decoding instructions for trace cache resume state in system passing decoded operations to both trace cache and execution allocation module
    20.
    发明授权
    Decoding instructions for trace cache resume state in system passing decoded operations to both trace cache and execution allocation module 失效
    解码指令，用于跟踪缓存恢复状态，系统将解码的操作传递到跟踪缓存和执行分配模块

    公开(公告)号：US07181597B2

    公开(公告)日：2007-02-20

    申请号：US11217707

    申请日：2005-08-31

    申请人： John Alan Miller ,  Stephan Jourdan

    发明人： John Alan Miller ,  Stephan Jourdan

    IPC分类号： G06F9/06

    CPC分类号： G06F9/3808 ,  G06F9/3824 ,  G06F9/3826

    摘要： A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A first copy of the operations is passed from the decoder to a build engine associated with a trace cache. The system and method further provide for passing a second copy of the operation from the decoder directly to a back end allocation module such that the operations bypass the build engine and the allocation module is in a decoder reading state.

    摘要翻译： 管理处理器指令的系统和方法提供增强的性能。 该系统和方法提供用解码器将第一指令解码为多个操作。 操作的第一个副本从解码器传递到与跟踪缓存相关联的构建引擎。 该系统和方法进一步提供将操作的第二副本从解码器直接传递到后端分配模块，使得操作绕过构建引擎并且分配模块处于解码器读取状态。